CMOS Wideband Continuous-Time Sigma-Delta Modulator

Continuous-Time Sigma-Delta (CTSD) Modulator is one of the most important directions of the Anolog-to-Digtal Converter's (ADC) development, because it will achieve high bandwidth and low power at the same time. It would be widely applied in wireless and video areas.A wide bandwidth and low power continuous-time sigma-delta modulator is designed under SMIC 0.18-um CMOS process. The work includes system design, circuit design, and layout design. In this paper, we make a glance at various type of ADCs, and conclude the advantages and disadvantages of the continous-time Sigma-Delta ADC. A series of nonideal effects from the circuit level are considered in the system level design, such as the finite dc gain of the opamps, the finite unit gain bandwidth of the opamps, non-zero loop delay, the variation of the RC time constant, clock jitter, as well as the nonlinearity of the DAC. In the circuit level, the compensation of the integrator could reduce the effect of the finite unit gain bandwidth of the operational amplifier. In other wards, it could save power at the same speed. In addition, the adder and quantizer are combined together through the Gm cells and resistive ladder, which could work well in high frequencies. And a highspeed comparator is designed for the loop delay requirement. Through the system level simulation, we could decide how much linearity is required for the DAC, and then we could choose the suitable sizes of the current cell through some process parameters. On the condition that the clock frequency is 200MHz and the oversampling rate is 20, we choose a single loop structure with 3 order noise shaping and 4 bit quantizing. The simulation results show that this modulator reaches the signal bandwidth of 5MHz and the dynamic range of 75dB. Its overall power consumption is 20mW under the 1.8V power supply.