Research On Key Technologies Of Low Power Continuous Time Sigma-Delta Modulator

With the popularity of the Internet of Things,people's requirements for communication are getting higher and higher,so 5G technology has been developed rapidly.Analog-to-digital converter(ADC)is an important part of communication chip.Because of its high performance and power requirements,low power and wide bandwidth Sigma-Delta ADC has become a hot research direction.Traditional Sigma-Delta ADC mostly uses Flash ADC based on voltage domain quantization as sub-quantizer.This structure needs a large number of comparators based on operational amplifiers to achieve high speed and high precision,which will consume a lot of power and area.With the reduction of CMOS feature size and the decrease of power supply voltage,it is very easy to obtain faster switching speed and higher transistor integration density,but it also makes the design of high performance analog circuits such as operational amplifiers difficult,and the voltage domain quantization analog-to-digital converter is no longer applicable.Comparatively speaking,digital circuits have achieved faster speed and lower power consumption with the improvement of technology.The most important thing is that the time domain resolution has been significantly improved.This provides a conversion idea for low power design,that is,to convert voltage domain quantization into time domain quantization.This paper combines the advantages of time-domain quantization and Sigma-Delta modulator.In order to realize time-domain quantization with low power consumption,a time-domain quantizer based on ring oscillator is adopted through multi-comparisons.Based on the mathematical model of VCO,the feasibility of phase-domain quantization is analyzed.Simulink is used to build a behavior-level model to simulate and verify the feasibility.The results show that VCO quantizer not only realizes quantization function,but also has the characteristics of first-order noise shaping,which meets the requirements of Sigma-Delta modulator.In order to improve the linearity of VCO,this paper analyses the mathematical model of the delay unit of ring oscillation,and finds that the delay of each unit is related to its charging and discharging current.Based on this,a linear voltage-current conversion circuit is designed to control the delay of each delay unit with mirror current,and then control the frequency of ring oscillator.Considering that the frequency of the ring vibration is sensitive to the mismatch of the delay element,parallel connection is adopted to reduce the nonlinearity introduced by the mismatch.The simulation results of transistor level circuit of VCO quantizer show that it has relatively good performance as quantizer.In order to reduce the influence of nonlinearity on the performance of the modulator,it is necessary to reduce the nonlinearity of the current rudder DAC,because the nonlinearity introduced by the DAC can not be shaped by the loop.According to the analysis,improving the output impedance and reducing burr current are the key factors to improve the non-linear performance.In order to improve the output impedance,a gain-lifting circuit is used to further improve the output impedance of Cascode current mirror to reduce the fluctuation of output current.In order to reduce burr current,a set of isolation tubes were added between the switch and the output tube to isolate kickback,and the high-low cross buffer was redesigned.The output control voltage swing was controlled by the threshold loss of the MOS tube to further reduce burr current.The simulation results of the transistor level circuit of the current rudder DAC show that its output current has a good waveform.Based on Simulink's modeling analysis,the circuit of transistor-level loop filter,VCO quantizer and current rudder DAC are built,and a complete continuous-time Sigma-Delta modulator is constructed.TSMC 65 nm process is used to simulate and verify the results.The supply voltage is 1.2V,the working frequency is 640 MHz,the signal bandwidth is 20 MHz.Spectre simulation and FFT analysis of the data show that the SNR is 83.2d B,the SNDR is 76.1d B,the effective digit is 12.34 bit,and the power consumption is 12.3m A,which achieves a relatively good performance.