Research On Reconfigurable Testing Schemes For Mid-Bond 3D SoC

When users use devices with chips,they want the chip to provide as much functionality as possible in the smallest possible way,which leads to the chip being overintegrated and requiring more test data per unit area for testing than ever before.The increase in the amount of test data will lead to a longer time during 3D chip testing and the resulting increase in power consumption,further leading to a sharp increase in test costs,which poses a huge challenge for 3D chip testing.To reduce test costs,this paper investigates the reduction of test data storage and test time as follows:An improved run length encoding compression method for 3D chips is proposed.First,in order to reduce the proportion of determined bits in the test cube,a partial inputreduction was performed on the test cube;then,a variable-length-segment compression was performed on the processed data to improve the utilization of codeword in the encoding table;and finally,a coding method is designed according to the frequency of the run-length,and the flag bits are encoded with tri-state signals,and a hardware structure for data scheduling between different dies of 3D chip is designed.Experimental results show that the compression method in this paper has achieved a high compression rate,with an average compression rate of 74.39%,which is better than other similar compression methods,while the area overhead is not significantly improved.A reconfigurable test method for 3D chip binding based on interlayer compatibility and intralayer compression is proposed.Firstly,in order to improve the compatibility of the test vectors in different layers of the 3D chip,the layout of the core which is most favorable for the compatibility of the test vectors is found by using the fast convergence of the genetic algorithm.Then,according to the compatibility of the test vectors,a reconfigurable hardware structure is designed to test the compatibility vectors,and the test data is compressed again.Compared with the non-reconfigurable test method,the test time is reduced by 55.40%,and the test compression ratio is 81.89%.