Test Data Compression Method Of Mixed Fraction And FDR Code

Integrated circuit has been regarded as the heart of electronic products since its birth.Driven by market demand,System-on-Chip(So C)has occupied the leading position in integrated circuit design.Chip is not only applied to daily life,but also an important technology supporting the aerospace,communication and new energy.Chips have more and more diversified functions inorder to meet market demand,the integration becomes higher and higher.As a result,the amount of test data expanded,and the test situation becomes more and more serious: the test time is longer and the cost is higher.The storage space,operation frequency and transmission channel of automatic test equipment(ATE)are limited,which can't afford the huge amount of test data.However,the application of chips in important fields puts forward higher requirements for it's quality.Therefore,it seems that screening high-quality chips through testing is a necessary and important step.So,looking for low-cost and efficient test methods has been the goal of chip testers.At present,design for testability and test data compression are two kinds of methods that can effectively alleviate the test problems.Design for testability is to add test hardware when designing the chip,so that the chip can complete self-test internally and free the test from the ATE.However,the additional hardware overhead makes this method fails to achieve the goal of low-cost and high-efficiency.Test data compression is compresses huge test-data to the range that ATE can afford,so as to increase the speed of data transmission,reduce test time and cost.Coding methods are usually used to compress test data,among which the coding methods based on run length,run correlation and probability statistics are selected by more people in the actual test.Based on the coding compression technology,this thesis combines run length coding and run correlation coding,proposing an improved coding compression method,compression method of mixed fractional and FDR code.Firstly,considering the law of run-length,the continuous run sequence is stored as fractions,and FDR is used to encode the numerator denominator and the length of the original test data,which effectively improves the low efficiency of short run-length compression,at the same time,it can reduce the number of encoding.The run-length with poor correlation that can't be converted into fraction is coded by FDR directly,which gives full play to the inherent advantages of FDR code in test data compression and makes the coding more flexible.Compared with the single coding and compression method,this hybrid coding method needs significantly less coding times and saves a lot of test time.This thesis selects ISCAS89 standard circuit for compression,the results show that the compression rate of this method is relatively stable,varying from 45.9% to 75.3%,and the average compression rate reaches 61.0%.Combined with theoretical analysis,the feasibility of this method is further verified.For the same test set,the compression rate of this method is increased by 11.9% compared with FDR code,17.6% compared with Golomb code and 16.9%compared with binary algorithm.