Fine-grained and coarse-grained architectures for two-dimensional discrete wavelet transform

The purpose of this study is to design efficient architectures both for fine- and coarse-grained processing of 2-D Discrete Wavelet Transform (DWT) in real-time applications. Architectures based on processing individual datum on every cycle are categorized as fine-grained or sequential architecture. In coarse-grained architectures, two or more datum can be processed simultaneously providing a faster implementation solution for 2-D DWT. 2-D DWT is the focus of this study since the image data itself is in 2-D plane. Also, the additional computation can provide a higher compression ratio than in 1-D transformation.;A semi-systolic array is designed as a fine-grained architecture. It has the minimum computational units possible for a full-word computation. It can be applicable to any convolution that requires an arbitrary sub-sampling function. The semi-systolic array presents a better implementation of the convolution function of DWT, offering higher efficiency than regular systolic implementation when applied for 2-D DWT. The semi-systolic architecture has an efficiency of at least 91% which increases proportionally to the number of octaves demand in an application, with no change in the architecture design except for minor modifications to the control logic and total memory size. The semi-systolic architecture is scalable for different sizes of filters and different numbers of octaves. It also incorporates distributed memory to local processing units to limit the communications to the nearest neighbors and reduce the routing complexity. This semi-systolic architecture is a very good candidate for VLSI implementation.;Although the semi-systolic architecture designed in this study has a faster computational time compared to most of the available architectures found in the literature, it is not enough for high-resolution and real-time video applications. Two models of coarse-grain computation are studied to improve the processing time of the 2-D DWT for real-time applications. Two coarse-grained architectures, Parallel-Sequential and Sequential-Parallel, are proposed. The first one offers a moderate gain over the fine-grained architecture with proportional increase in hardware cost. This is achieved by combining two different types of filters, the semi-systolic filter implemented in the fine-grained architecture and a new version of a parallel filter. The second coarse-grained architecture offers a higher improvement with a significant increase in hardware cost. This coarse-grained architecture is mainly implemented with the new version of the parallel filter introduced in the moderate coarse-grained architecture. The gain in computational power of both coarse-grain architectures is significant for consideration in real-time application. The increase in hardware cost of both coarse-grained architectures is not extremely large to pose any problem to its implementation in silicon with the current available technology. These architectures are designed to be scalable for different filter taps and octaves as in the sequential architecture.;Chapter 1 contains a brief section on the history from the beginning of representing a function to the recent Discrete Wavelet Transform, motivation of this study, and finished off with a discussion on Discrete Wavelet Transform itself. Chapter 2 contains analysis of several related filters, fine- and coarse-grained architecture implementations found in the literature. Chapter 3 contains discussion of the proposed work on the Semi-Systolic Filter Architecture, operation, and implementation. Chapter 4 is devoted to both coarse-grained architectures. Chapter 5 discusses the VLSI implementation issues of both types of architectures. Conclusion and future work is given in Chapter 6.