Research On Characteristics Of A High Reliability Planar Static Induction Transistor

Static induction transistors（SIT）is a kind of power device which has been developed again in recent years.Because of its high withstand voltage,large current capacity,good radiation resistance and other advantages,people gradually pay attention to it.For a long time,power devices working in the field of aerospace are facing the threat of high-energy protons,heavy ions and various kinds of radiation from the space environment,which are prone to radiation effects,and their performance is seriously affected or even burned out.This paper mainly studies the failure mechanism of the single-event burnout（SEB）of the static induction transistor,including theoretical analysis,device simulation,simulation of the factors affecting the SEB and the test of the electrical properties of the trial samples of the static induction transistor.The main contents are as follows:Firstly,the development history of static induction devices and the influence of space radiation on power devices are described.The typical structure of static induction transistor is introduced.Finally,the planar type buried gate（PTBG）structure of static induction transistor（SIT）is chosen as the research goal of this paper.Secondly,the working principle,the formation of potential barrier and the photoelectricity effect when the transistor is radiated are analyzed.The cell parameters of the device are determined and the electrical characteristics are simulated,including static electrical characteristics and dynamic electrical characteristics.When the breakdown voltage BVDSS is 580 v,the pinch-off voltage VP is-5V,the specific on-resistance Ron is 29.4Ω·mm²,the turn-on time ton is 11.3ns,and the turn-off time toff is 4.5ns.Thirdly,The SEB effect of the static induction transistor is simulated.The model and parameters are determined.The anti-SEB simulation comparison between the buried gate type static induction transistor and the vertical double diffused metal oxide semiconductor field effect transistor（VDMOSFET）is made.The SEB failure mechanism of SIT is analyzed by comparing the SEB effect failure mechanism of VDMOS.The simulation results show that the breakdown voltage of the drain source is 580 v and 660 V for SIT and VDMOS,respectively.When the gate off voltage is-10 V,the critical drain voltage of the SEB of SIT is 440 V,which is much higher than 230 V when VDMOS is off.The drain current of sit is 10^-3A/μm when SEB occurs,and the drain current of VDMOS is 10^-4A/μm when the SEB occurs,The buried gate type SIT has more advantages than VDMOS in resisting the SEB effect.Furthermore,the failure mechanism and influencing factors of the SEB effect of the static induction transistor are analyzed.The electric field and potential distribution before and after the SEB effect are studied,and the possible influencing factors are simulated The critical drain voltage of the SEB of the static induction transistor under different gate bias voltage is obtained.Theoretically,the conditions for improving the SEB of the static induction transistor are obtained.It includes increasing the thickness of epitaxial layer,reducing the carrier lifetime,and reducing the width between two gates.Finally,the electrical characteristics of the SIT sample are tested,including static and dynamic electricity characteristics.For the follow-up single event test to complete the preparatory work.Final results are as follows: drain and source breakdown voltage BV_ds is 530 V,gate and source breakdown voltage BV_gs is 30 V,on-resistance R_on is 75mΩ,drain saturation current is 11 A,t_don is 26.8ns,t_r is 85.2ns,t_doff is 29.2ns,t_f is 52.2ns.