Simulation Research On Single Event Burnout Hardening For SiC Power MOSFET

With the rapid development of science and technology,the electronic power system has an urgent demand for power semiconductor devices with high power,low power consumption and the ability to use various harsh environments.The third-generation wide band gap semiconductor material,silicon carbide(SiC),has the advantages of wide band gap,high critical electric field,high saturated electron rate and good thermal stability.It is a key material for the development of high performance and high reliability power semiconductor devices.SiC has a bright development prospect.With the rapid development of space exploration technology in China,spacecraft widely using power semiconductor devices are prone to single event burnout effect(SEB)when operating in the space radiation environment,which affects the reliability and even shortens the life of spacecraft.Based on the above background,this thesis studies the trigger mechanism of SEB effect of SiC power MOSFET devices,and studies two more feasible anti SEB hardening methods,in order to improve the anti SEB performance of SiC power MOSFET devices without sacrificing the static electrical characteristics of the devices.First,this thesis uses Silvaco TCAD simulation software to simulate the structure of 2300 V SiC power VDMOSFET device,and introduces the static electrical characteristics and physical mechanism of the device in detail with the simulation curve.Then the physical model and material parameters used in the simulation are introduced,and the validity and accuracy of the physical model and material parameters used in the device simulation are verified by comparing the simulation results of the relevant structures with the actual measurement results of the streamer.Secondly,this thesis introduces the relevant parameters of single event effect simulation and SEB effect simulation of SiC power VDMOSFET device,studies the trigger mechanism of the device and the performance characterization of heavy ion sensitive incident position,and then introduces the conventional SEB hardening scheme of power MOSFET device and the strengthening idea of this thesis.In this thesis,a reinforced structure of SiC power UMOSFET device against SEB effect is studied.The simulation results show that the multi-layer buffer layer structure can effectively adjust the internal electric field in the drift region to avoid severe collision ionization at the drift region/substrate high and low junctions.N-type polysilicon structure can reduce the instantaneous power density by modulating the electric field in the drift region,and can also change the direction of hole flow to reduce the possibility of triggering parasitic bipolar junction transistors,At the same time,this thesis also discusses the influence of the depth change of N-type polysilicon on the anti SEB performance of the device in detail,and describes the process flow of the reinforced structure in detail,and introduces the feasibility of the process.Finally,this thesis also proposes an anti SEB hardening structure for SiC power VDMOSFET devices.The simulation results show that the highly doped P+ region and the channel source structure in the hardening structure can effectively reduce the hole concentration in the device and avoid the generation of high temperature points at the metal/SiC interface in the source region.At the same time,this thesis also discusses in detail the influence of the source buffer layer doping concentration on the device lattice temperature and the metal/SiC interface temperature,The process flow chart of TSID-VDMOSFET is introduced in detail,which proves the process feasibility of the reinforced structure.