A Study Of High-speed Serial Interface Based On JESD204B Standard

Design of new type integrated circuit has higher requirements on converter's resolution,which promotes the continuous increase of conversion rate and leads to the situation that the existing interface circuit, such as CMOS, LVDS, can not meet the demands of converter's development. Design of the interface circuit that will be used to support higher speed converter has become a new problem to be urgently solved in integrated circuit design. According to above requirements, this paper designs a high speed serial interface circuit, which meets the JESD204 B standard and the highest speed can be 12.5Gbps.The high speed serial interface circuit designed in this paper is a gigabit serial data link that connects the converter and receiver(FPGA ? ASSP or ASIC). By using the Ser Des technology, the new special link is generated on original basis, thus to simplify the interface link from the converter to receiver(FPGA?ASSP or ASIC).The high speed serial interface circuit applies the method of adding control characters and end characters to make data packing on the input end, so as to form a series of 8 frame data,applies the automatic synchronous scrambler module of which the polynomial is1+X14+X15, to reduce the spectrum peak phenomenon and data errors. This paper establishes the special data link layer based on the JESD204 B standard; applies the initialization of frame synchronization, synchronization of initialized channel,deterministic latency, monitoring and calibration with frame alignment and other methods,to improve the transmission accuracy of the whole data link. At the same time, it also applies the 8b/10 b coding and decoding method for data encoding and decoding, and generating a special control character, so as to realize the channel alignment monitoring and maintenance.This paper establishes a complete system design model and explains the design method and function of each module, determines the alternate form of data before and after passing each module. This paper applies the Verilog hardware description language to achieve circuit design and carries out circuit simulation verification and result analysis. This paper designs a JESD204 B high speed serial interface circuit that connects the two 14 bit of250M ADC and FPGA. It gives out the design model of this interface circuit and the simulation results of ideal function. The interface supports the subclass 1 of JESD204 B standard, supports the deterministic latency and backward compatible subclass 0. It can also support the scrambling mode, of which the highest speed can be 12.5Gbps.Compared with CMOS, LVDS and other interface circuits, such a interface circuit that is based on JESD204 standard simplifies the overall system design, reduces the system cost,which makes the design of circuit board wiring more easily; changes the high pins low speed parallel interface to low pins high speed serial interface, smaller IC package. The interface is more in line with the industry's requirements of higher speed, more channels and better resolution, and this interface can be easily extended to meet the requirements of future bandwidth.