High-speed SerDes Transmitter Interface Design Based On JESD204B Protocol

Nowadays,the resolution,sampling rate and number of supported channels of the new data converter(ADC/DAC)are increasing,and the power consumption of the design is getting lower and lower.The data transmission rate inside the chip was reached several gigabits per second.The traditional CMOS and LVDS interfaces were no longer suitable for high-performance new data converter,the way to solve this problem is to develop a new high speed interface circuit.Therefore,JEDEC solid state technology association released JESD204 B international universal serial interface standard,which was used to connect data converter and its interconnection.The standard supported deterministic latency and multi-channel synchronization,the data transmission rate of single channel could up to 12.5 Gbps.Compared with the traditional CMOS and LVDS interface,the number of output pins were greatly decreased,the design costs and power consumption were saved.On the basis of further study of JESD204 B protocol,the thesis designs a transmitter circuit based on JESD204 B protocol using 65 nm CMOS technology.The circuit supports sending two channel four 14 bit 250 MSPS ADC data,the data transmission rate of single channel can up to 10 Gbps,supports subclass 2 mode in JESD204 B protocol and subclass 0 mode in downward compatibility,and supports deterministic latency and multi-channel synchronization.Firstly,this thesis introduces the development process of JESD204 B protocol,analyzes its advantages and development prospects.Then detailedly describes the transmitter content in JESD204 B protocol,mainly includes the transport layer,scrambling module,the data link layer and 8B/10 B encoding module,the RTL design and function verification of each module are completed.The transport layer organizes14 bit parallel data outputted by the four ADC into 64 bit data and send them to two channels for transmission by adding control characters.On the basis of further study of parallel scrambling/ descrambling principle,designs a four bytes parallel scrambler with bypass ability and supports big/little endian mode based on JESD204 B protocol,the scrambler can optional enable/disable scrambling,and different modes can be selected according to different requirements.The transport layer consists of three parts: code group synchronization(CGS),initial link synchronization sequence(ILAS)and userdata,which are generated by state machine.By analyzing the principle of 8B/10 B encoding,and deeply study the inherent correlation between K code and D code,an improved encoding scheme combining the K code and the D code is put forward.The method is simpler,faster and takes less resources of FPGA than the traditional methods.Finally,according to the protocol requirements,independently completes the RTL design of the transmitter circuit.Using Quartus II 13.1,a development tool of Altera(Intel),and Modelsim to verify the correctness of transmitter function and the comprehensibility of the code.The received user data is parsed according to the definition of the receiver protocol.After verification,the data restored by the receiver is exactly the same as the data input by transmitter.