Design Of High-speed SerDes Interface Based On ESIstream Protocol

At present,the data converter(ADC/DAC)is developing towards the direction of high speed and high precision,and the data transmission rate of the chip is gigabit per second(Gbps).Early ADC/DAC usually used parallel transfer technology as the input and output ports of data,such as CMOS interface and LVDS interface.However,the parallel transfer technology was beginning to fail to meet the technical requirements of the current high-speed ADC/DAC,so the JEDEC solid state technology association developed a high-speed serial interface standard JESD204 B.Although the interface standard has been developed for more than ten years and the ADC/DAC using the interface has been widely used in various fields,the application of the interface technology in military,medical,electronic countermeasures,aerospace and other special fields is not favorable due to its complex technical standard,high link delay and difficulty in hardware implementation.To solve this problem,UK company E2 V has developed and released a new high speed serial interface standard ESIstream(Efficient Serial Interface).The interface designed by this standard has the advantages of simple circuit structure,low link delay and higher data transmission efficiency.On the basis of in-depth study of ESIstream protocol,this thesis adopts 65 nm CMOS technology to design and implement a circuit based on ESIstream protocol.The single channel data transfer rate of the interface circuit is 6.4Gbps,which supports deterministic delay and multi-channel synchronization.This thesis first introduces the common interface technology of data converter,and analyzes the advantages and development prospect of ESIstream interface compared with traditional interface technology.Then,the content of ESIstream protocol is analyzed in detail,including 14B/16 B code technology,scrambling technology,link synchronization technology,multi-channel synchronization technology and deterministic delay technology.Based on the deep understanding of ESIstream protocol specification,an implementation method suitable for 14-bit ADC/DAC protocol layer regenerator circuit is proposed.The 14B/16 B code algorithm is adopted to reduce the complexity of digital circuit design and increase the effective data rate to 87.5%.LFSR uses Fibonacci structure and polynomial (317+ (33+ 1 parallel design,which reduces the clock frequency of LFSR compared with serial design.The final designed circuit completed the function verification of the receiving end and the sending end on Modelsim,and integrated the circuit with TSMC 65 nm process on the Design Compler platform.The results showed that the circuit could work normally at 400 MHz and reach the transmission speed of 6.4Gbps with a single channel under the conditions of all constraints.