Design And Implementation Of PCS Layer In Multiprotocol High Speed Serial Interface Chip

With the rapid development of the digital age,the importance of the data is increasingly reflected.In order to realize the value of data,the transmission process is extremely important.In the face of high-speed and stable transmission requirements put forward by massive data,high-speed serial interface technology has emerged with its good characteristics.However,the core technologies are mainly in the hands of foreign countries.The practice of directly purchasing IP cores or chips to build system networks is widely used in the country and it has formed an excessive reliance on foreign markets.Especially in the important military fields,the lack of technical accumulation has seriously threatened our own security and development.This project is based on the high speed serial interface technology,and strives to design a multi-protocol high speed serial interface chip,which is of great strategic significance for promoting the development of domestic independent R&D products in this field.This article mainly focuses on the FC protocol and 10 G Ethernet protocol,and refers to the FC-AE-ASM standard and 10Gbase-R standard,respectively,to complete the design and implementation of the PCS layer.The difficulties that need to be solved are: the stability issues in the high speed data transmission,multiple types of coding and decoding issues,high speed data scarambling/descrambling issues,the data bit-width conversion and synchronization issues,and complete FPGA verification issues.As for the above difficulties,this paper has done the following research.Firstly,an improved elastic buffer based on traditional FIFO is designed.Properly insert or delete the IDLE character provided by the protocol,the read/write speed of the FIFO become adjustable to make the data stably spread across the clock domain and to solve the high-speed transmission stability issues.Secondly,as for the different requirements of 8B/10 B and 64B/66 B,the 8B/10 B adopts a step-by-step operation method,which is performed in two steps of 5B/6B and 3B/4B.The 64B/66 B uses the look up table method to divide the data and control code to solve the problem of different types of codec.Furthermore,the principle of serial scrambling/descrambling is improved and the parallel method is adapted.The problem of high-speed data scrambling/descrambling is solved and the data rate is guaranteed.Then,with the method of the least common multiple rule and fractional frequency division,the 80B/32 B and 66B/32 B bit width conversion problem is solved.Detect the data state and align the data frame headers to the boundary to complete the data synchronization problem.Finally,the IP core GTY provided by FPGA is used to construct the loop verification platform for PMA and PCS layers,and a complete set of clock solutions is proposed.It overcomes many engineering problems in FPGA verification and the layer is fully verified.