Design And Implementation Of VLSI Architecture For LDPC Channel Decoder Based On 5G RedCap

In recent years,with the development of the Internet of Things,assisted driving,wearable intelligent devices and other fields,the requirements for wireless communica-tion technology have gradually increased.In order to achieve low latency and high reli-ability communication,channel coding technology is currently the best solution.At the3GPP RAN1 87 meeting held in 2016,it was preliminarily determined that the e MBB data channel encoding would use LDPC（Low Density Parity Check）^[1]code.With the freez-ing of the 5G R17 standard in June 2022,LDPC code stood out among channel encoding schemes such as Turbo code,becoming the channel encoding scheme for 5G NR（New Radio）and 5G Red Cap（Reduced Capability）.LDPC code was born in 1962 and has a development history of more than 60 years.However,due to the limited technical level of the time when it was proposed,and the high complexity of the BP（Belief Propagation）decoding algorithm used,the code was not given much attention at the beginning.With the introduction of the simplified BP decoding algorithm,namely the MSA（Min Sum Algorithm）decoding algorithm,LDPC has emerged in the field of vision of researchers.This thesis takes the BP decoding algorithm as the research starting point,deduces the BP decoding algorithm based on mathematical formulas,and derives the principles of several existing decoding algorithms based on the order of algorithm complexity from complexity to simplicity.After a detailed analysis of the complexity and performance of each decoding algorithm,a layered scheduling based LLR（Log Likelihood Ratio）BP decoding algorithm is selected as the research basis for the improvement direction of this thesis.Although the above algorithms outperform the BP decoding algorithm based on flooding scheduling in terms of performance,their throughput performance is not satisfac-tory.If a fully serial decoder architecture is used,the algorithm cannot meet the throughput requirements of 5G devices.Therefore,the mainstream improvement solution is to use a partially parallel decoder architecture.However,due to the interlayer data dependency of the hierarchical scheduling method,its hardware efficiency is relatively low.Therefore,this thesis chooses another improvement scheme,which is the fully serial LLR BP decod-ing algorithm based on hybrid scheduling,as the direction of algorithm improvement.Considering the performance gain of LLR BP decoding algorithm due to the introduc-tion of offset factor,this thesis first adds offset factor to the algorithm,which improves the block error rate performance of the algorithm without increasing complexity.At the archi-tecture level,due to the use of a hybrid scheduling method that is compatible with flood-ing and hierarchical scheduling,flooding scheduling is used to update the check nodes that originally needed to wait for inter layer conflict data updates,which improves the through-put performance of the decoder.At the same time,a decoupling mechanism is introduced in the update unit of the check node to adapt to the pipeline output of the decoder.At the fixed-point level,this thesis determines a set of optimal fixed-point parameters through multiple iterative simulations.Under the condition of meeting protocol throughput,the decoder has a certain performance gain compared to the layered scheduling LLR BP de-coder architecture.In order to further improve the throughput performance,after studying the degree distribution of the base matrix specified in the protocol,the original number of check equations was reduced,and the throughput was increased by about 10%while the performance loss of block error rate was almost negligible.Finally,based on Matlab and Modelsim software,the functional simulation verification of the decoder was com-pleted.Under a 250 MHz clock,when the lifting size is 384,the base matrix is the first one,and the bit rate is 1/3,the throughput of the decoder can reach 565.92 Mbps,which meets the protocol requirements.Furthermore,using the DC（Design Compiler）platform and the TSMC（Taiwan Semiconductor Manufacturing Company）28 nm process library,the decoder was logically synthesized,providing resource consumption information,And it was verified that there were no violations in the timing of the module.