Encrypted IP Core Research On Ahb-lite Bus Transmission Data Based On FPGA

Data encryption and information protection have been widely used in civil and military fields such as smart homes,medical research,and national defense security.Currently,this technology is mainly implemented in two types of platform,namely software platform and hardware platform.The hardware implementation is more practical and more complicated.On the one hand,although the software is flexible in data encryption,the efficiency of encryption and decryption is low,and FPGA hardware is used to process data in parallel,which is more suitable for processing massive data in the era of big data;On the other hand,the risk of virus destruction and theft is increased year by year,and FPGA hardware technology is more suitable for protecting data during data processing.The current symmetric encryption algorithm and asymmetric encryption algorithm were analyzed in the first part of this thesis.By introducing the problem that data is easily intercepted by hackers,brute force cracking,and intentional tampering during data transmission,the advantages and disadvantages of commonly used encryption algorithms are introduced.A comparative analysis was conducted to select the appropriate AES symmetric encryption algorithm for these problems,and the advantages of the RSA algorithm were used to complement and improve.In terms of hardware implementation,based on the basic principle of AES encryption algorithm,Verilog HDL(Hardware Description Language)is used to sequentially implement the algorithm's byte substitution operation,row shift operation,column mixing operation,and round key addition operation.Combined with the RSA algorithm,the defects of the AES algorithm that are easy to be intercepted and cracked are improved,and finally the data is sent and received through the digital envelope technology.Secondly,in order to improve the utilization efficiency of hardware,a pipelined design is adopted for the AES implementation part.In this thesis,the FPGA development environment in Quartus II 13.0 was used to complete the design of encryption and decryption IP in the EP4CE115F29C7 chip of Altera.In the selection of the bus,the AHB-Lite bus is finally adopted by comparing the current mainstream bus in the industry.The AMBA bus protocol is studied,and the interface design between modules in the protocol and the transfer of IP are analyzed,which improves the versatility of the IP core designed in this thesis.So as to achieve the intended design purpose.Finally,the hardware design of the algorithm,analysis,layout and routing of the modules were implemented in the FPGA development application platform;in order to test the performance of the design,running the test by writing Testbench,using Quartus software and Modelsim simulation tools for timing analysis and verification,and encrypt Statistics of the speed and error rate,the timing results verify the reliability and feasibility of the design,and achieve the intended purpose of the design.