Design And Verification Of Low-power CAN2.0 Bus IP Core For SEP6210 Chip

Controller Area Network(CAN)is one of the most widely used field bus,CAN IP has been gradually integrated into Embedded microprocessors that related to Internet of things and other fields.At present,many domestic and international IC design company engaged in the research and development of CAN IP,so there are a variety of CAN IP products in the semiconductor market.Southeast University Suzhou Integrated Circuit and System Key Laboratory rely on National ASIC System Engineering Research Center,and mainly research on micro-controller solutions of Internet of Things.Due to the strict restrictions of the field,it requires a lower power consumption.Suzhou Integrated Circuit and System Key Laboratory have developed a CAN IP core in the early years,But power consumption of the CAN IP has been unable to meet the current needs,Total power consumption of the CAN IP in normal work mode is 17.2mW,and it did not design low power mode,IP core must be working for long time.However power consumption is extremely harsh for lot chip,it simply can not meet the power requirements.In order to solve the above-mentioned power consumption problem,this paper puts forward the design and implementation of low power CAN IP for SEP6210.This paper designed a specific solution to reduce power by analyzing the power consumption of integrated circuit.First,global gated clock were designed to control sub-module of CAN IP which are not necessarily work for long time.Part of the global gated clock can be controlled by the control register,while the other part is automatically opened or closed;second,five work mode were designed to meet the needs of different application scenarios;Third,added dynamically clock to CAN IP,that is,to reduce the working clock frequency to reduce power consumption when it don’t need high performance.In this paper,it deals with the low power design of CAN IP RTL level code,and ultimately integrated the CAN IP into the SEP6210 chip.The paper also finished the function simulation,FPGA verification and power analysis.System-level simulation shows that CAN IP implements the functions specified by the CAN 2.0 protocol.The results of FPGA verification shows that the CAN IP transmission rate can reach 1Mbit/s and is compatible with 500Kbit/s and 250Kbit/s transmission rate;Power analysis results show that total power consumption of the CAN IP is 13.1mW,the CAN IP power consumption decreased by 23.8%compared to the old CAN IP.In general,the design index of the CAN IP have reached the expected requirements.