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Design Of A High-speed Low-power AES Information Security Chip Based On The AMBA Bus

Posted on:2011-10-09Degree:MasterType:Thesis
Country:ChinaCandidate:C M ZhangFull Text:PDF
GTID:2178360302491338Subject:Software engineering
Abstract/Summary:PDF Full Text Request
With the development of information technology, information security becomes more and more important. However, because of the progress of cryptanalysis and integrated cireuits, the popular encryption algorithm of DES is not capable of meeting the demands of new applications, so it is valuable to research the algorithm and implementation of AES, Advaneed Eneryption Standard.Firstly, The author analyzes the encryption and decryption algorithm about AES and then discussed the equivalent inverse cipher and keyexpansion procedures.Seeondly, a high-speed and low-power scheme for AES is proposed and implemented in this paper. Then, the simulation,synthesizing and verifying results are provided. In order to design a high-speed AES core, the thesis adopts a mixed pipeline structure with both inner-round pipeline and outer-round pipeline. The author designs a core that can operate on a frequeney of 125MHz and the corresponding throughput 2466.3mbps. on the other hand, considering the hareware cost, The author adopts a hardware resource-shared structure for encryption and decryption modules. Inaddition, the thesis improves the design methods for several transformations of the algrothm to reduce the hardware cost. For example, The author adopts the field transformation to design sbox and byte-level structure to design MixColunms and InvMixColurnns transformation. The final hardware gate counts of The AES core is 102.1K, which is a extremely high hardware efficiency. Form the two aspects above, in sum, The author design a high-performance and low-power AES chip.Thirdly, The author provide a scheme to design an other IP core based on AHB bus interface is designed. This IP core is used to connect The AES IP and AHB IP so that the AES IP core can be integrated into those SOCs with AMBA bus easily.Finally, The author finish the logic synthesis, STA, place&rount and DRC/LVS of the AES design, also surmmarize and discuss the work in this Paper, point out the deficiencies to improve and advance the new research direction and contents in the future.
Keywords/Search Tags:AES, low-power, resource-shared structure, pipeline, AMBA bus
PDF Full Text Request
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