Research And Design Of Digital LDO

In recent years,with the rapid development of integrated circuit design,portable electronic devices have also become popular and popular.More and more functional modules are integrated in a system on a chip,which puts forward higher requirements for the power management module inside the system.Low-dropout linear regulators(LDO),as an important part of power management IC,have also developed rapidly.The traditional LDO structure is mainly an analog circuit design,using an error amplifier and a large size MOS tube for feedback adjustment.However,the reduction in the feature size of the chip makes the requirements on the operating voltage lower and lower,and when the power supply voltage drops below the threshold voltage,the gain of the amplifier will fail to meet the design requirements,which will cause the performance of the analog LDO to decrease.All-digital LDO(DLDO)has been widely explored by more and more designers in this case.The traditional all-digital LDO circuit used a comparator,shift register,and MOS tube array for negative feedback adjustment.In recent years,the structure of all-digital LDO circuit has been increasingly innovative,in order to solve the traditional structure output ripple,transient response,and load dynamic range issues.This design used a ring oscillator VCO to convert the analog voltage to a pulse width;the time-to-digital conversion circuit TDC was used to convert the pulse width into a digital signal;the digital PID structure was used as the control module of the DLDO,and the output compensation effect was achieved by controlling the switching of the PMOS tube array;the MOS tube array was improved on the basis of a typical design to solve the pulse spikes generated during the adjustment process.Finally,a fully digital low dropout linear regulator circuit with low operating voltage,wide load dynamic range and fast response was designed.This design was based on the CSMC.18 process,using Cadence tools for circuit and layout design,and simulation testing under the ADMS hybrid imitation platform.The layout area of the final design is 0.125mm~2;the input voltage range is 1V-1.8V,and the output is 0.6V-1.2V;the load current range is between 10mA-800mA.When the circuit operating voltage is 1.2V,and the load current alternates between 200mA-300mA,the transient response time of the DLDO at 0.8V regulated output voltage is 0.786?s,the undershoot is 456mV,and the maximum current efficiency is 99.835%,the maximum power efficiency is 96.507%.When the frequency is 1KHz,the power supply voltage suppression ratio is-42.6dB.When the frequency is greater than 3MHz,the power supply voltage suppression ratio is higher than-30dB.When the operating temperature and process conditions change,the output voltage error is within±1%.