Research And Implementation Of Direct Bitstream Digital Coding Technology

In digital audio technology,the traditional pulse code modulation(PCM)technology mainly improves the signal-to-noise ratio(SNR)by increasing the number of quantization bits,which obviously puts forward very high demands on the performance of the back-end analog circuit.The direct stream digital(DSD)coding technology can achieve very high SNR with only single bit of quantization.At the same time,this technology can alleviate the complexity of the back-end analog circuit.So,it is a research focus in digital audio technology.This dissertation focuses on the DSD coding technology and the design of digital-to-analog conversion circuit.The main contributions are as follows:(1)To solve the problem that the near-end(20kHz~200kHz)noise power of the low-rate DSD signal is too large and the output SNR is reduced,a digital interpolation algorithm based on DSD signal is proposed.The single-bit DSD signal is firstly converted to a multi-bit DSD signal by a digital low-pass filter(LPF).Then,the sampling frequency of the multi-bit DSD signal is increased by interpolation.Finally,the multi-bit DSD signal is restored to a single-bit DSD signal by a Δ-Σ modulator.The simulation and hardware test results show that the nearend noise power of the DSD signal after interpolation is significantly less than that of the original DSD signal;and the spectrum of the two signals are consistent in the baseband(0~20kHz),so the accuracy of the signal remains.(2)The theoretical research and hardware implementation of the Δ-Σ modulator are carried out,and a third-order Σ-Δ modulator with single-bit quantization is designed and implemented.By optimizing the zero point and pole point of the noise transfer function(NTF)of the modulator,the SNR and stability of the modulator are improved.Finally,the structure coefficients of the modulator are further optimized by the root locus method,which limits the output amplitude of the integrators in the modulator and greatly reduces the difficulty of hardware implementation.Simulation and hardware test results show that when the bandwidth of the input signal is 20 kHz and its sampling frequency is 22.5792 MHz,the peak SNR of the modulator can reach 146 dB,and the effective number of bits is about 24.(3)Theoretical research and hardware implementation of the post filter are carried out.The post filter mainly includes a semi-digital finite impulse response(SDFIR)filter and a fourth-order active analog LPF.The effect of clock jitter on the performance of SDFIR filter is studied by modeling the clock jitter.Simulation and hardware test results show that the SDFIR filter has good performance against clock jitter.At the same time,in order to solve the problem that the even harmonics exist in the actual hardware circuit,a differential circuit is given to effectively suppress the even harmonics.After the design of the digital-to-analog circuit is completed,the hardware test is carried out,and the test results show that when the amplitude of the input signal is 50% of full-scale(FS),the SNR of the final output analog signal can reach about 90 dB.