Research And Implementation Of LDPC Encoder And Decoder For Satellite Burst Communication

With the wide application of satellite communication in military and civilian area,satellite communication technology is developing towards multitask,broadband and high reliability.The technology of channel coding is to ensure the reliability of communication.Low density parity check code(LDPC)is a high reliability channel coding technique.LDPC is widely used in satellite communication.Limited by the volume and power factors of spaceborne devices,making full use of the channel resources of satellite channels to dynamically adapt to different channel environments,the low complexity LDPC encoder and decoder with variable code length and multibit rate has become a research hotspot in recent years.Based on the application of satellite communication,this thesis study the LDPC encoding and decoding technology with multi rate and variable code length.The encoder and decoder studied in this thesis support longer code length,support burst communication,low hardware complexity and high throughput.In this thesis,the study of codec is carried out in four aspects: reducing complexity,supporting multi mode,satisfying throughput and supporting burst communication.First,based on the pseudo random LDPC structure defined by a standard,the basic matrix generation algorithm and the encoding and decoding algorithm are given.Secondly,based on the idea of zero storage of parity check matrix,a coding algorithm based on row dynamic generation is proposed.Compared with the basic coding algorithm,This algorithm only costs a small amount of time delay of the clock.,and saves large storage resources.Thirdly,in order to guarantee the BER performance of the decoder,a piecewise linear fitting decoding algorithm is proposed.this algorithm based on the logarithmic domain SPA algorithm,and the logarithmic operation is transformed to linear operation,which reduces the complexity of the decoder.By rationally dividing the domain and range of the excitation function,the algorithm achieves the ideal error performance.Finally,the Verilog hardware description language is used to design and implement the codec in the VAVIDO environment,and the zc706 development board is used to verify the encoder and decoder.The encoder realizes the multimode and throughput requirements by reasonable design of the parallelism.Based on two phase decoding structure(TPMP),the decoder takes the throughput index and burst index into consideration,and achieves the decoding performance by reasonably dividing the number of nodes.The test results show that the encoder and decoder ultimately support the 14 mode,the maximum code length is 16352,and the BER performance accords with the given index in the reference standard,and the throughput is greater than 100 Mbps under the worst case.