Simulation And Research Of Electrostatic Discharge Protection In Intergrated Circuit

Along with the constant development of the semiconductor technology, feature size of the semiconductor device scaled down and more complicated device structures appeared in chips. The smaller feature size and the new appeared structures bring some new problems. The design of electrostatic discharge (ESD) protection devices becomes more and more different. The smaller feature size means thinner gate oxide, smaller voltage that gate oxide can endure. The new structures may also results in disappearance of common ESD protection devices. Thus, the design of ESD protection devices should follow the development of semiconductor technology.In the beginning of the thesis, some basic concepts of ESD and ESD protection devices were introduced. In this part, the model and test methods of ESD and the principle of basic ESD protection devices, such as resist, diode, MOSFET, and SCR, were included.Secondly, we simulated the ESD protection ability of the mentioned basic devices by Technology Computer Aided Design (TCAD) tools.The carrier distribution, electric field distribution and impact ionization of the devices under the ESD events were obtained from the simulations. Process parameters were adjusted to observe the effect of substrate concentration on the trigger point of GGNMOS.To solve the heat problem comes from the ESD protection of SOI technology devices, we presented a. new novel structure. The effectivity of the new structure was validated by the device simulations. New problems arising from the design were analyzed and the corresponding solutions were introduced.All work of this thesis is based on device simulations with TCAD.The results will be useful for the design of the ESD protection device, especially for the ESD protection of SOI technology.