Verification Of SMBus Interface Based On UVM

With the rapid development of integrated circuits,the integrated rate and complexity of chips are increasing.The difficulty,workload and importance of verification are also rising rapidly.Verification runs through the whole chip-design process.In general,its workload accounts for 70% to 80% of the whole design and development process.And it becomes an important factor,which have an effect on the time to market and r&d cost of chips.Digital IC chip verification is mainly divided into digital front-end function verification and digital back-end timing verification.This paper mainly studies the core of digital IC verification: front-end function verification.This paper analyzes the present mainstream Verification language System Verilog and Universal Verification Methodology(UVM),and studies the advantages of System Verilog as well as UVM class library map,tree structure and other important mechanisms.Taking SMBus interface as the research object,this paper analyzes the SMBus protocol and summarizes the basic characteristics and transmission mode of SMBus.Based on analysis of SMBus interface design requirements,the overall structure of SMBus interface is designed,and the internal modules are illustrated in detail.Taking SMBus interface as the research object,this paper analyzes the SMBus protocol and summarizes the basic characteristics and transmission mode of SMBus.Through the analysis of SMBus interface design requirements,the overall structure of SMBus interface is designed.Verilog was used to complete the design of SMBus interface,and the internal modules were analyzed.According to requirements analysis and UVM verification methodology,the overall structure of SMBus interface validation platform was designed,and the functions of each component were determined.The System Verilog verification language and UVM verification methodology are used to write various verification components in SMBus validation platform in a hierarchical way.It mainly includes general parts: the interface that connect the measuring SMBus with the verification platform;the sequence that generates the test incentive;the sequencer that sends the sequence to the driver;the driver that drives the incentive to the interface;the monitor that detects and packages the data from the interface and sends the package to the reference model;the reference model that immitate the function of the DUT;the scoreboard that test the correctness of the DUT;the function coverage to measure the verification progress,etc.All this can improve the reusability of the verification platform.Utilizing the TML transaction-based communication method to realize the communication between each component,and reduce the dependency between them.Moreover,it can improve the efficiency of the verification platform.After completing the construction of the verification platform,this paper summarizes and list the functional points on the basis of SMBus design specifications,which needed for verification.At this point,the compilation of various testcases is completed.The simulation tool VCS was used to debug the verification platform,simulate and make regression test to the DUT.In addition,it can collect code coverage and function coverage,and generate coverage report,then realize the monitoring effect on the verification progress.In this paper,System Vrilog and UVM verification methodology is used to build SMBus verification platform,write a variety of test incentives,through the reciprocating supplement,modification and testing,code coverage and function coverage rate has reached 100%,completed the verification work of SMBus interface.In addition,the verification components are written in a hierarchical way,and the communication between components is realized through the TML port,which improves the reusability and efficiency of the verification platform.