The Design And Implementation Of A Self-biased Phase-locked Loop Applied To Serial Transmitter

With the advent of the information age,people's demand for information keeps increasing.The fast and stable communication system becomes more and more important to people's life,and it has become a hot spot of research.The clock inside the communication system is inseparable.In order to obtain a stable clock signal to meet the demand,the most commonly used method is to use phase-locked loop circuit to generate the clock signal.The phase-locked loop can be used for multiple frequency,frequency division,data drift suppression,frequency tracking,jitter filtering,and phase control.In addition,it can also be used for clock recovery circuit to recover clock and data.The performance of the phase-locked loop has a direct impact on the quality of its output clock signal.Low-noise,high-precision,wide locking range and fast locking of the phase-locked loop have become a common goal of researchers.The phase-locked loop described in this paper is an important module in the serial transmitter for Ser Des.When the serial transmitter works,it is usually used together with the receiver chip.When sending data,the transmitter converts the parallel data into a high-speed serial differential data stream output.At the same time,it can also act as the receiver and receive the signal sent by the sender.The module designed in this paper is mainly used to generate internal clock signal and assist in parallel and serial conversion of data.The design is based on the self-biased phase-locked loop with charge pump.The self-biased phase-locked loop is a kind of phase-locked loop.The difference is that it does not need a separate external bias module.The loop bandwidth of the self-biased phase-locked loop designed in this paper can follow the change of frequency and realize the frequency tracking function.In this paper,It first to analyze the circuit principle,component module and linear mathematical model of second-order and third-order phase-locked loops.The influence of some main loop parameters of phase-locked loop on the performance of phase-locked loop is summarized.Research has been done to improve noise performance,improve loop stability,and reduce lock time.In the circuit design,the circuit structure is reasonably adjusted to eliminate the dead zone effect in the circuit,and the stability problem is solved by rationally designing the loop filter parameters.The circuit adds the initialization circuit to reduce the lock time and ensure the normal start-up of the voltage-controlled oscillator.The self-bias circuit is designed to solve the bias problem of the charge pump and the voltage-controlled oscillator.Based on the principle of counter,a 1/7 frequency divider with duty cycle of 50% is designed.Finally,the output signal frequency of the whole circuit is seven times that of the input reference signal.In the process of simulation verification,the sub-module circuits of the design are simulated and verified,and the whole circuit is verified by the whole simulation.The overall loop was modeled using Verilog A to verify its stability.According to the phase-locked loop transfer function,the noise transfer function of each sub-module and the noise of each module are obtained by simulation.The total noise curve is fitted by Matlab.Finally,the layout of the entire circuit is rationally designed and laid out,and postsimulation verification is performed.The self-biased phase-locked loop designed in this paper adopts SMIC 0.18 um CMOS technology,realizes maximum jitter less than 90 ps,locking time less than 12 us,and power consumption less than 28 m A.The phase margin is about 60 degrees.In addition,the PLL designed in this paper has good noise performance.