The Research And Hardware Emulation Of Quasi Cyclic LDPC Code

The generation and development of Low-Density-Parity-Code make the modern communication technology development into a new level. As we all known, the ultimate aim of communication technology is obtain reliable communication using effective power that approximating Shannon limit, and it is provided with this excellent performance. The LDPC code is widely applied in satellite communication, deep space communications and the fourth generation mobile communication system and other fields in the reliable information transmission at present.Firstly the paper introduces the communication system and some basic knowledge of the channel coding theorem, then drawn LDPC code. It is begin with the definition of LDPC code, making the system research and the elaboration for the LDPC code representation methods and constructing method, especially the structure of quasi cyclic code., furthermore, it analyzes the performance in coding and decoding.Secondly we studied several common coding algorithm for LDPC code, and corresponding compared and discussed the cyclic code and quasi cyclic code coding with special structure, furthermore analyzed the good performance of the two classes codes and it was easy to hardware realization advantages.Then it studies focus is LDPC code of various decoding algorithm, including probability BP decoding algorithm, LLRBP decoding algorithm, RBP decoding algorithm and the VCRBP decoding on the basis of such algorithm. Through the simulation results the algorithm prove its superior performance. Furthermore, The paper completed its hardware LDPC code decoding simulation in DSP chip of TMS320DM6446experiment development box. The process including each module design and code optimization.Finally, this paper prospects further improvement and development for the LDPC code.