Principles Of The Codec For LDPC Codes And Its Hardware Implementation

LDPC (Low-Density Parity-Check) codes are a class of capacity approaching linear block codes, even outperforming Turbo codes if the LDPC code is long enough. Although LDPC codes exhibits lower decoding complexity and lower error floor, the relatively high encoding complexity poses a great challenge to their application in practical communication systems. With the development of hardware technique, however, it is possible to achieve reliable communications over various channels with low encoding as well as low decoding complexity.In this dissertation, some key problems of Low-Density Parity-Check (LDPC) codes are investigated with theoretical analysis and computer simulations. The main aspects are summarized as follows:The basic principles and methods of LDPC coding/decoding are introduced. Based on the relationship between the error floor of LDPC code and its hamming distance, a new searching method for the minimum-weighted codewords is developed, which facilitates the performance and error floor analysis of LDPC codes. The feasibility and effectiveness of this new method are testified under certain specific cases.The LDPC codes in the CCSDS standard are discussed and their permance simulated. According to the CCSDS standard, the coding procedure is coducted based on the parity check matrix. This paper proposes a modified coding scheme for the hardware implementation, reducing the memory requirement of the encoder. As for the decoder, the widely used normalized MSA decoding algorithm is adopted. The message passing and storage in the hardware implementation, however, is modified according to the special parallel structure of the parity check matrix, greatly saving the hardware resource.