Research And Design Of High Linearity Ultra-Wideband Low Noise Amplifier Based On SiGe BiCMOS

Software radio technology can concentrate multiple functional modules such as Bluetooth,WLAN,GSM and GPS on a single chip.This technology can cover all working frequency ranges required by these modules,which promotes the miniaturization process of the device and reduces the cost of chip design.The RF receiver system is undoubtedly an important hardware support for software radio technology,and the low noise amplifier,as the front-end module of the RF receiver,plays an important role in the whole system.This article is based on the JAZZ 0.18um SiGe BiCMOS process and aims at designing two versions of high-linearity ultra-wideband low noise amplifier circuits operating at 0.3-4GHz.The first stage of the first version of the circuit in this paper uses resistive negative feedback and cascode structure to achieve wideband input matching and good gain flatness,and use the zero point peaking technique to raise the high frequency gain to provide a margin for the high-frequency performance degradation that may occur in the layout parasitic.In order to increase the input 1dB compression point,a derivative superposition technique is adopted,that is,the auxiliary common-emitter transistor that is biased at a lower base voltage is used to eliminate the transconductance's third-order nonlinear term of the common-emitter transistor in the cascode structure,the second stage adopts the emitter follower structure for wide-band output impedance matching and improve reverse-phase isolation.In order to avoid the deterioration of linearity,the operating current of the emitter follower is biased to a larger working current state through the biasing tube.The metal resistance in series with output is used to compensate the real impedance of the output resistor;the second version of the circuit uses a noise cancellation structure with two branches,and the first branch is also a cascade structure with resistance negative feedback.In order to superimpose the signal of the second branch and eliminate the noise phase,the source follower realized by the NMOS transistor transmits the useful signal and the noise to be eliminated.The tube,simultaneously,provides a resistive load to the second branch.The second branch is a common-emitter amplification structure using a zero-point peaking technique and a derivative superposition technique.This stage uses an NPN BJT as an amplifying tube and an NMOSFET as a load tube,even under the same operating current,a higher voltage gain is available.And the output impedance of the source follower is used for output impedance matching.The post-simulated performance of the first version of the circuit after the layout design and parameter extraction is:17dB<S₂₁<17.8dB,2.7dB<NF<2.82dB,IIP_1dB is-9.4dBm,power consumption is 41mW,and the input and output impedance are well matched.The post-simulated performance achieved by the second version of the circuit is17.3dB<S₂₁<17.7dB,2.63dB<NF<2.86dB,IIP_1dB is-8.9dBm,power consumption is33mW,and the input and output are well matched.In general,the post-simulated performance of both versions of the circuit can meet the requirements of the index,and leave sufficient margin for the performance degradation that may occur in the actual chip manufacturing process.