Research And Implementation Of Receiver Circuit Based On JESD204B Protocol

In the era of Internet of things,with the gradual upgrading of data intensive applications and the rapid increase of data transmission rate in communication network,the interface performance between converters and logic device has become a key factor affecting the integration of high-speed system.The existing CMOS or LVDS parallel interface technology cannot meet the current design requirements of high-resolution and high sample rate converters.Joint Electron Device Engineering Council issued JESD204B serial interface protocol in 2011.Compared with parallel interfaces,the serial interface based on JESD204B protocol has the advantages of low power consumption,few pins and high flexibility.It has become the mainstream in the field of high-speed data transmission.Through the in-depth study of JESD204B protocol,the receiver circuit in line with the protocol is designed in this paper.It is used as the interface of a 2.5 GSPS,16 bit DAC to realize the high-speed data transmission.Firstly,the circuit design index and the overall scheme of the receiver circuit are formulated according to the project requirements.On the basis,the specific link configuration parameters and link working mode of the application layer is set.By analyzing the working principle of self-synchronous type,parallel descrambler design scheme with"double enable"control signal is proposed.The enable signals are applied to the input and output ports of the descrambler respectively,the synchronization of descrambling function and data is ensured.A three-level data mapping structure of transport layer is proposed for ten link working modes of the receiver circuit,which simplifies the mapping logic of transport layer deframer in multi-link mode.The RTL design of link establishment,decoder,control character restoration,frame/lane synchronization monitoring and other modules is conducted with Verilog HDL.The preliminary simulation verification is completed.Secondly,A UVM verification platform is built to verify the designed receiver circuit with the SPI and JESD204 VIP provided by Synopsys.While completing the verification of link establishment and data transmission process under different link working modes,VIP error injection mechanism is used to simulate the process of transmitting invalid data from the transmitter to the receiver to ensure the perfection and reliability of the design.Finally,all testcases passed the VIP protocol check.Then,based on a 65 nm CMOS process library,the designed JESD204B receiver circuit is logically synthesized by using the Design Compiler software of Synopsys.The results show that the receiver circuit can work at the frequency of 312.5 MHz under the typical environment.The circuit occupies 152444.88μm~2logical resource area and the total power consumption is 69.29 m W.On this basis,the layout of the DAC integrated with the receiver circuit is designed and optimized.The layout area of the digital circuit of the DAC is about4125×916μm~2。Finally,a test platform is built to test the DAC at the board level to evaluate the actual performance of the receiver circuit.The test results show that the receiver circuit designed in this paper can support ten link working modes and realize the simultaneous operation of eight channels.The circuit meets the working mode of subclass 1 in JESD204B protocol s.It can be applied to 2.5 GSPS and 16 bit DAC chip.The single channel serial transmission rate can be up to 12.5 Gbps.Compared with the domestic related research,the receiver circuit designed in this paper can be interconnected with the transmitter interface of different logic devices,and has advantages in data transmission speed.