Design And Implementation Of EMMC Array Storage System Based On FPGA

With the rapid development of the global electronic information industry, the requirement s of the storage devices are becoming higher and higher, not only the requirements of highspeed data transmission, but also the need to continuously improve the storage capacity. Mobile phone, tablet, camera, military electronic equipment and other mobile terminal require their own sizes as small as possible, these mobile terminals have higher and higher requirements on the volume, capacity and speed of their storage devices. Therefore, it is quite necessary to design a compact, high-capacity, fast-speed, strong-compatibility of storage devices.According to the requirement of the background, the paper designs a eMMC array storage system based on FPGA. The array storage system is multiple relationships of individual chip system on the bit width and storage capacity, by way of an array increasing capacity and access rate to meet the growing demand for capacity and speed, its capacity comes to 512 GB. This design uses eMMC as the storage medium, which is small enough to more stringent requirements on the volume of electronic equipment. Based on the design of FPGA, with the eMMC’s advantages of compatibility, the design has higher portability. In order to achieve the above goals, the following work has been done:1. According to the system requirements, using 8 chips of single Micron eMMC memory chip, a Virtex-6 series of Xilinx FPGA, combined with a variety of power chip and clock module, according to the requirements of circuit design, this paper designs the hardware system.2. In-depth study of e MMC protocol, according to protocol requirements, summed the command sequence to control chip to read and write, using the ISE development tools based on Verilog HDL language to achieve eMMC controller with some design of state machine, so that the host can read and write to the e MMC.3. In order to send the needs of read and write to the controller of the chip to implement the read and write, the bridge between the master device and the e MMC chip must be designed. In this case, four level cache mechanism needs being custom. For the reading process, it caches the data from the e MMC’s read, then transfers to the GTX, after highspeed transmission, It finally returns the read data to the host interface. For the write process, cache data from the host and trans to GTX, after processing, it sends the data to the e MMC controller interface, then the data is written into the memory chip, completing the write process.4. Using the IP core – GTX Transceiver Wizard to custom GTX module, adjusting timing relationship, the FIFO interface is used to connect the host and eMMC devices to transmit data.5. Using ISim software debugging tools to debug each module’s function and timing design,and then gradually increasing the number of modules, debugging two modules and even more to test the communication between the modules until all except the controller and GTX module work properly. Using Chip Scope as hardware online debugging tools to debug controller module and GTX module to test communication function, and finally integrating all modules together to test the system’s overall ability. At last this paper designs an array storage system with capacity of 512 GB, and speed of 400MB/s in interface transmission.