Research On Physical Design Of DDR? Memory Controller And Soft Error Technique

With the rapid development of aerospace technology,the demand for anti-irradiation integrated circuits is increasing.The DDR memory controller is an important module inside the integrated circuit and is a bridge between the system chip and the memory bank.Soft errors are the main cause of chip failure in the space environment.Therefore,it is very important to study the physical design and soft error reinforcement technology of DDR memory controller.Based on the SMIC40 nm CMOS process,this paper completes the layout design of the 400 MHz DDRII memory controller.Using the hierarchical design method,the DDRII memory controller is divided into three modules: DDR top layer,data_slice and DLL,which solves the problem that the EDA tool runs too long and the number of iterations is too long during the design process.Through reasonable planning of the layout,adjustment of the power network scheme,and setting of module constraints,a large amount of congestion in the DDR top-level routing process is solved.The clock balancing problem of the clock signal to the data_slice module is solved by manually planning the clock network and adding inverters.By using the useful skew of the clock network,the method of setting the insertion delay to the timing unit clock port greatly reduces the timing convergence difficulty of the data_slice module.Timing verification of the DDRII memory controller layout was performed using static timing analysis.In order to solve the problem of functional reliability of DDRII memory controller under different working conditions,the timing verification is carried out under different process angles such as process,voltage and temperature.For the timing violations that occur during the timing verification process,the ECO method is used for repair.In order to ensure that the final netlist of the DDRII memory controller is consistent with the initial netlist function,a functional equivalence check is performed.The DRC,LVS,and Antenna inspection results show that the physical design of the DDRII memory controller reaches the acceptance criteria.Based on the completed DDRII memory controller layout,this paper proposes a selective circuit unit reinforcement method and constructs a soft error generation model.Using the method of image analysis,the sensitivity of the trigger in the circuit is obtained.The soft error experiment is repeated by scripting,and the trigger with higher sensitivity coefficient is selected.The soft error reinforcement of the DLL module is completed by the method of selective replacement of the radiation resistant standard unit.The analysis results show that the selective circuit unit reinforcement method can achieve soft error reinforcement without affecting the circuit performance.