Netlist Based EDA Physical Layout Comparision

With the development of chip manufacture and higher and higher requirements to electronic products by people,chip becomes more and more complicated today.The number of transistors integrated into one chip usually reaches thousands of millions.The complex of chip leads to complicated chip design,requiring longer design cycle and more design time.In the fierce competition of electronic products,the time of chip design to market becomes shorter and shorter,designing a complicated but functional correctly in short time becomes more and more difficult.Issues occur inevitably.With the emergence of new technology,and smaller manufacture technology,migrate existing chip designs to use the latest technology becomes usual.In EDA software,the algorithms of placement and route are NP.It takes days or hours to run once of them.This also brings great challenge to design chip works well in short time.The analysis of physical layout provides very important information to narrow down chip design issue of backend.For issues met during chip design,normally,chip designers check the suspected region in EDA tool,and then execute placement and routing algorithm to try to resolve the issue.It usually needs many cycles to solve the issue finally.It is error-prone to analyze the entire physical layout including tens of millions of physical elements manually.And much time is used for checking the correctness of analysis.In this thesis,a solution that can entirely or partly find differences for chip designer between two similar physical layouts or same physical layout of two different versions quickly is introduced,a script for eliminating difference between two physical layouts is provided also.It takes only minutes to complete the entire comparison of two complex physical layouts including tens of millions of physical elements.Chip designer will analyze differences generated,find the reason why issue occur,and run placement or routing tool or scrip for eliminating difference to resolve the issue.Different from the traditional way,chip designer only needs to analyze difference of two physical layouts instead of entire physical layout,so that reduces the amount of data for analyzing,the time for running placement and routing tool,and cycles for narrowing down the issue.Chip designer also could specify the running of comparison algorithm to specified area or some of specified physical elements,so that the amount of difference generated could be less and analysis could be more accurate.In this thesis,logical comparison is conducted by using name match for finding out logical elements that are logically equal.And then physical layout comparison is performed.In the first step of physical layout comparison,physical elements are classified using physical attributes and stored into tree liked data structure firstly,tree-liked data structure in target physical layout is iterated,and tree-liked data structure in input physical layout for physical elements with same physical attributes is searched.In the second step of physical layout comparison,geometry attributes comparison using coordinate of physical elements is performed.For algorithm of comparison,two optimization ways that cache a search path in tree-liked data structure of inputted physical layout and assigned different memory pools for child nodes of tree-liked data structure and physical elements are introduced.