Research On Building Routing Resource Graph And Routing Algorithm Of Virtex-5 FPGA

The application of FPGA chips in various fields is more and more extensive,and the products change rapidly.Commercial FPGA development environment supports the complete process of design input,synthesis and mapping,layout and wiring,simulation verification,bit stream file configuration.Academic research on FPGA mainly focuses on improving the efficiency of layout and routing algorithm,and the development process is still in the routing stage.VTR toolset is the main development environment in academia.It can support relatively simple chip structure,fewer types and numbers of logic blocks,simple and regular wiring resources,and can not be applied to the development of complex and resource-rich commercial FPGA chips.The difficulties of academic tools in dealing with commercial chips are chips modeling,wiring resource mapping and wiring.We introduce the FPGA computer aided design flow in academic field,and compare the academic FPGA models and commercial FPGAs.Then,we model the Virtex-5 FPGAs and accordingly build the routing resource graph.(1)Firstly,when making model for the FGPAs,we add new attributes to the academic model on the basis of the VTR toolkit,which describe the spatial domain,complex logic blocks and irregular wiring resources in the commercial FPGAs.(2)When building routing resource graph,we merge the open source tool Torc and expand the VTR to support the processing of newly added information and finally build the accurate routing resource graph.Subsequently,we need to check the newly built routing resource graph to verify its correctness.(3)Finally,we improve the VTR Path Finder algorithm so that it can route circuits on the routing resource graph.We have modeled the Xilinx Virtex-5 FPGA.Based on the routing resource graph,we have also implemented the improved routing algorithm.In the experiments,we test the routing algorithm using MCNC standard benchmarks and large scale VTR benchmarks.Compared with the results of ISE,the average running time of the selected experimental benchmarks in the routing stage is 35.27% longer than ISE,with 25.82% longer critical path delay and 21.96% longer wire length.