Research And Implementation Of Routing Algorithm For Test Chip Design

Although the VLSI industry has entered nano-scale era and even approached very close to the end of Moore’s Law, it is still in its rapid development. Resulting in continuously decreasing process dimensions, the design rules are more complex and these unprecedented challenges lead us to design more efficient test chips to ensure yield. The current test chip scale is expanding rapidly, and with the coming of16nm or even smaller process nodes, more number of test structures are needed to deal with increasing new process defects. The routing problems of these test structures are also becoming more complex.In this paper, a new routing process for the development of the test chip design is proposed, after analysis of state-of-the-art VLSI chip routing technology. Innovation and improvements of this new process are as following:1) A specific routing algorithm between two points is proposed in this thesis. By means of a new concept of "boundary expansion", the paper presents a new point to point wiring path search algorithm. With the definition of "free nodes", this algorithm expands the boundary and will not terminate until find out a path or determine that no solution is available. The theoretical and experimental comparisons show that the algorithm can solve the routing problems with lower complexity.2) A multi-step process is used instead of the single algorithm based process. The test chip routing problem is split into two phases, namely global routing and detailed routing, in which each step uses technologies such as pattern routing and monotonic routing to accelerate the process. The routing time has been shortened to15%-25%of the original. The reliability and availability of this process has been verified in several manufacturers’test chips.