Design Of Network-no-Chip Structure And Implementation Of Routing Algorithm Based On FPGA

The rapid development of multicore chips has brought huge impact on the performance of the communications among nuclears.On-chip networks solve the issue of global clock and power consumption using the way of packet exchange which improves the performance of communication.We propose the routing algorithm which is suitable for implementation on chips for the two common topologies.Besides,we also propose a new kind of topology.We design an adaptive routing algorithm for the Mesh network which is based on the traditional routing deterministic dimension-ordered routing algorithm.This algorithm can adjust the routing policy dynamically according to the jams in the links.After implementing the function modules of the node,we can package them into a complete routing node.Assembling the routing nodes into 4*4 Mesh Network can test the perfoamance of the algorithm.There are too many loops in the Torus network.The solution of traditional virtual channel to the deadlock is not good for on-chip implementation.We design a lock-free algorithm for symmetric Torus network which is based on the E-cubes routing algorithm for the multidimensional structure.This algorithm takes up less resources and is easy to implement,because there is no virtual channel.This thesis proposes a new topology called H-annular Mesh through the analysis of the disadvantages of Mesh.The topology adds links from the apex nodes to the center nodes based on the strcture of Mesh.We also design an adapative algorithm for this topology.According to the results of comparision between 6*6 H-annular Mesh network and Mesh network,the average routing hop of Mesh is 4.2 and the average routing hop of H-annular Mesh is 3.1.The transmission delay is relatively shortened by 33.67%.The result shows that H-annular Mesh network do improve the ability of the interaction among the nodes.Building hardware test platform,we implement a 4*4 Torus type network embedded with the lock-free algorithm on Virtex-5 FPGA.Through the test of communication among the inter-nodes and calling IP cores,the routing algorithm achieves the desired goals.