Research On Routing Resource Graph Generation Technology In VTR

The FPGA design flow includes circuit design,synthesis,technology mapping,packing,placement,routing,bitstream generation and downloading.In academic field,the VTR tool set are the main FPGA computer-aided design(CAD)tools,while ISE and Quartus II are two main commercial FPGA CAD tools.Basically,the traditional VTR tools use an simple island FPGA chip model and supports the entire FPGA design flow except for bitstream generation.Additionally,the simple FPGA model does not includes the detail information of FPGA.As a result,the VTR tools can not be used in the commercial field.Therefore,we construct a new FPGA chip model for the detail device information on based of VTR tool set,and accordingly extend the VTR tools to process the device information.Meanwhile,we also make a research on FPGA bitstream generation techniques with the support of related tools in ISE.Based on the traditional VTR CAD flow,we study the Xilinx commercial FPGA architecture,and model the FPGA chip with a structured description language.This model includes the detail device information within FPGA,such as complex modules,irregular wires and airspace.According to the FPGA model,we modify the VTR tools to support the process of the detail device information,and add new functions to export and import the routing resource graph.By studying the XDLRC document which describes the chip information,we extract the correspond physical names of the input/output pins,various wires and other device resources within FPGA.With the relevant interfaces in the Torc tool,we can directly configures the pins,wires,and other resources in the chip,so that the VTR tools can be applied in the commercial chip structure.Based on the VTR,taking the XDL file as an entry point,we expand VTR to support FPGA bitstream generation.The main technologies include FPGA chip modeling,routing resource graph generation,and XDL file synthesis.Finally,we develop a software platform,and confirm the functions of each tool by experiments.The experimental results show that our tools support synthesis,technology mapping,packing,placement and routing for the commercial FPGA,but there is still room for improvement in performance.Compared with ISE,the tool's running time exceeds 64%,and the critical path delay exceeds 55%.