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Pre-processing Technology Of FPGA Routing Resource Graph

Posted on:2018-12-10Degree:MasterType:Thesis
Country:ChinaCandidate:F GaoFull Text:PDF
GTID:2348330518998946Subject:Computer software and theory
Abstract/Summary:PDF Full Text Request
FPGA CAD tools are divided into research and commercial type,compared to commercial tool,the research tool is less used,mainly focused on rising efficiency of the algorithm.Routing technology is a very important part of FPGA support software system,an effective method to describe the FPGA routing architecture for CAD tools is to create a Routing Resource Graph,which completely specifies all the connections that may be generated in the FPGA routing.Now the scale of integrated circuits increasing,routing graph generated form the existing research tools is small in size and simple in structure,and can not adapt to the commercial FPGA in resource and structure.Based on the deep understanding of FPGA CAD,a structured description method is used to model the commercial FPGA structure.Based on the existing FPGA description method,the simulation airspace label is added to enrich the academic description method,to simulate the areas where the current academic tools can not be simulated,and study deeply the complex resource blocks and describe the details of their internal connections in detail.After establishing the model,then based on the routing graph generated from the academic tools,a corresponding FPGA XDLRC document is exported with the Torc tool,the filtered wire information in that document is linked to the logic resource input and output pins in initial graph,and preserve the interface of the routing graph,modify its internals to represent the true graph that exists on FPGA.While a series of information on the graph node is updated to make it meet the rationality of the graph.Through modeling FPGA and pre-processing of the routing graph,the new routing graph is finally successfully provided to the router for routing.The experiment results show that the router using pre-processing graph has increase by 13% in run time compared to using initial graph,and keep value in delay time.
Keywords/Search Tags:FPGA, structured description, Routing Resource Graph, pre-processing technology
PDF Full Text Request
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