Design And Implementation Of Gigabit Ethernet MAC Control Verification Platform Based On UVM

With the increasing complexity of integrated circuit design and the rapid development of design scale,functional verification has become an indispensable part of chip design process.It is come from the market application project for core data processing and switching chip of the Internet of things of the author's internship company.The main task of thesis is to complete the functional verification of the gigabit Ethernet MAC controller.According to the protocol specification of DUV,the verification platform based on universal verification methodology(UVM)is designed.The main function of DUV is to complete the data frame transmission between the physical layer and the logical control sub-layer,and to complete the data burst transmission by DMA.The correctness of the function execution of DUV is reflected in the fact that the data of frame is not lost and the transmission is completed correctly.Therefore,the verification objective can be divided into three parts: GMAC function,data burst read-write function and data frame preprocessing.Only when all the verification objectives meet the requirements,can the design function verification be complete.Firstly,the verification plan is created according to the verification objective.In this thesis,the grey box verification method is adopted and checker mechanism about the monitor,assertion check item and comparator are designed.Each of submodules has checker to verify data frames and submodule's function operation.There are three parts of designing verification components in verification platform.The first part is interface driver component.according to the analysis of the interface protocol,DUV contains three clock domains in total.Therefore the clock and reset common components are designed for reusability.At the same time,the GMAC interface UVC,APB interface UVC and AXI interface UVC components are designed for reusability based on the classification of verification objectives,respectively simulating the Ethernet data frame behavior of physical layer,external system configuration behavior and data burst read-write transmission operation.The second part is configuration component,including register and data burst configuration component.The register model and two accessed mechanisms(front door and back door access)are designed to achieve register access and improve the verification efficiency.The other configuration component is about data burst transmission.The five transport channels are defined in axi_driver cache to support the transmission of AXI UVC.DMA UVC is responsible for external system initial configuration and memory allocation.The part of randomized configuration variables are defined in dam_cfg,and the rest configuration variables randomized in dma_driver,meanwhile all randomized configuration variables are sent to AXI UVC or register model by dma_driver.Part three is design of incentive component,the Ethernet layered protocol message generation component(ether_seq)is designed to support the generation of different types of four-layer protocol frames.On the verification platform built in this thesis,the incentive generating component can be simultaneously sent to the underlying drivers of GMAC UVC,AXI UVC and DMA UVC,effectively verifying the reusability of ether_seq.Finally,assertion check items and functional coverage groups are designed.Based on the above verification scheme,a hierarchical UVM verification platform is designed and implemented to complete the verification of gigabit Ethernet MAC controller.Coverage is an important measure of the completeness of functional verification and has a very important role in functional verification.Analysis of coverage results can effectively assess the progress of current verification efforts.For obtaining verification results in time and getting the coverage report of real-time monitoring,a coverage tracking tool based on verification plan is designed that named VPM(verification plan management).As can be seen from the defect curve generated by VPM,all defects were repaired as the verification cycle advanced.The code coverage rate of the final design to be tested is 91%,and the assertion coverage rate and function coverage rate reach 100%.Combining the waveform analysis and coverage result,it can be seen that the current test function points have all completed the design requirements.