Design And Verification Of Dual-gigabit Ethernet MAC Based On DMA

At present, Ethernet is most widely used. The increasing requirements of network bandwidth and speed are also for the requirements of Ethernet throughput. On one hand, the transmission rate of a single channel Ethernet MAC controller should be improved. On the other hand, the application of multichannel Ethernet MAC is able to increase the transmission rate of network without changing the structure of the Ethernet module in the system. Therefore, research on multichannel gigabit Ethernet MAC has very important practical value.The main technical problem of Ethernet lie in MAC layer and physical layer. This dissertation is mainly concerned with the design and verification of dual-gigabit Ethernet MAC that met IEEE 802.3 standard protocol. Dual-gigabit Ethernet MAC is compatible with 10/100 Mbps transmission rate by which a IP core is made.The dual-gigabit Ethernet MAC includes a DMA controller, two independent ETH0/ETH1 controller and dual proprietary bus interface. Data is transferde by DMA between ETH0/ETH1 controller and memory buffer as a data driving module. Dual proprietary buses are used to transmit and receive data between ETH0/ETH1 and DMA. 10/100/1000 Mbps half/full duplex operation is supported and a variety of Ethernet MAC packet processing functions is achieved by ETH0/ETH1 controller. The implemented module in this dissertation is suitable for SOC based on Core Connect bus structure, which has a PLB master interface used for data transmission, and has a DCR and OPB slave interface are used for configuration of registers.After the design is completed, the module-level simulation and system-level verification of Dual Gigabit Ethernet MAC is launched. During the process of module-level simulation, firstly, Core Connect bus functional model, CPR function model, the loop model and Frame_gen model are established. Then, 81 functional verification items based on the function feature are listed. Thus this plan has covered all the functions of modules completely. At last, all module items on the simulation platform are verified. During the System-level verification, functional models are replaced by IP core and formate the SOC by inter-connection of each other. Then,functional verification and interconnection verification for the dual-gigabit Ethernet MAC is processed as part of the SOC.