A Design Of Efficiency GMAC Verification Platform Based On UVM

With the increasing integration and functional complexity of integrated circuits,the workload and importance of verification is also growing throughout the chip manufacturing process.The traditional functional verification is to improve coverage by increasing the test items,the efficiency of this verification method is low and it is hard to transplant platform to the similar project,also will cost a lot of manpower and resources to affect the entire chip design cycle.It can be seen that the efficiency of verification is of great significance to the production of the chip.At present,there are a variety of verification methods in the verification area,but most of the methods to establish the verification platform are time-cost and not reusable.In these validation methods,the Universal Verification Methodology is the latest validation methodology officially introduced by Accellera in 2011^[1].It inherits the advantages of VMM and OVM and is the most advanced technology in the field of functional verification.UVM add the sequence components,objection mechanism and the callback mechanism on the basis of the mechanism of hierarchical idea of VMM and the factory mechanism of OVM to help developers shorten development cycles and improve code maintainability and reusability of design in other verification projects^[1].And,Gigabit Ethernet MAC is a widely used module in system-on-a-chip design.Therefore,study how to improve the verification efficiency of Gigabit Ethernet MAC play an important role in shortening the production cycle of on-chip system.The goal of this paper is to use UVM to design a verification platform with a short development time and a reusability to improve the efficiency of Gigabit Ethernet MAC verification.In this paper,we first compare the several methods of verification in the mainstream,select the method of UVM as the basis of design verification platform,and use the SystemVerilog language to write the verification platform.In the aspect of the structure of the verification platform,we use the structure of the UVM to solve the problem of modifying the traditional verification platform,and the shortcomings of the traditional verification platform are difficult to be used in other projects.In the design of verification platform components,this paper designs components such as drive,monitor,reference model,scoreboard,and register model according to the standards of the UVM,and uses the mechanisms specific to the UVM when designing the components Improve design efficiency and reusability.In the aspect of stimulate generation,this paper uses stimulate with constraints and uses the sequence mechanism in the general verification method to improve the design efficiency.In terms of coverage statistics,this paper adds the functional coverage group to the monitor component,and realizes the function coverage statistics of the verification platform.After running all the verification items,the coverage rate and functional coverage are analyzed statistically by the coverage statistics tool and the coverage under the same verification number as the traditional verification platform is compared and analyzed.The coverage ratio of this design is that the coverage of the verification platform is higher than that of the traditional verification platform,and the expected design goal is achieved.The drive components that have reusability are then added to the new verification platform for proper operation,verifying the reusability of the drive components.The verification platform designed in this paper has higher verification efficiency compared with the traditional verification platform,and the verification component in the platform has strong reusability and completes the design goal before design.