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Design Of Data Acquisition And High-precision Pulse Generation System Based On FPGA

Posted on:2020-07-19Degree:MasterType:Thesis
Country:ChinaCandidate:L J LiFull Text:PDF
GTID:2428330602450688Subject:Engineering
Abstract/Summary:PDF Full Text Request
Pulse generators are widely used in communication,testing and industrial control fields.The parallelism and low delay of FPGA make it become the ideal scheme for designing pulse generators.In this paper,a data acquisition and high precision pulse generation system based on FPGA is designed for high power microwave source.The whole system uses Intel FPGA chip,Quartus II as the development platform and Verilog hardware description language as programming language.The pulse generation system can generate four independent pulses to control the operation of the high power microwave source as a trigger signal.The frequency,number and pulse width of each pulse,and the relative delay time between the four pulses can be set by the host computer.The time delay design for the pulse uses the combination of FPGA counter and programmable delay line chip DS1124.The relative delay between the four pulses can achieve both a large dynamic range and a high resolution of up to 0.25 ns.The four pulses can be triggered by an external signal or controlled by the host computer,and the priority of external trigger is higher than the software trigger.The data acquisition system can collect data from 50us~200us microsecond signals with a sampling rate of 2MSa/s.In the logic design of the FPGA,a kind of circular RAM is designed,which enables the system to sample N points of microsecond signal before the trigger signal arrives and M points of microsecond signal after the trigger signal arrives.The data will be uploaded to the host computer through Ethernet immediately after one sample cycle is finished.At the same time,the data acquisition system also sample voltage signals and current signals of the four channels with a sampling rate of 1Ksa/s.In the Qsys development environment,W5300 controller is customized.The NIOS II receives the control command from the host computer by controlling the Ethernet chip W5300.The real-time state parameters of the high-precision pulse,monitoring voltage and monitoring current are uploaded to the host computer at the frequency of 50 Hz.
Keywords/Search Tags:FPGA, Data acquisition, Pulse generation, Circular RAM, Precise delay
PDF Full Text Request
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