Design Of Data Generation And Acquisition System Based On FPGA

With the development of emerging technologies like IoT,automatic drive,telemedicine and so on,the existing wireless communication cannot meet the transmission requirements of high speed and short delay.Millimeter wave frequency has higher carrier frequency and rich spectrum resources,which make it suitable for high-speed large broadband transmission.The research background of this thesis is based on the subject of millimeter-wave high-speed communication,which needs to measure the performance of the designed baseband algorithm in millimeter frequency band.Therefore,it is necessary to build a data generation and acquisition system that meets the test conditions.The baseband test signals are generated by the system.After signals are transmitted through the RF frontend and the test channel,the performance of the algorithm can be evaluated in the upper computer software through the recovery,storage and uploading of the signals.In view of different requirements of sampling rate,resolution,storage depth,channel number and interface type of data generation and acquisition system in actual engineering,two data generation and acquisition systems of high rate and medium rate are designed respectively in this thesis to meet the actual requirements.The two systems mentioned in this thesis are both designed based on FPGA.Among them,the high rate system has the update rate of 5GSPS and the vertical resolution of 16bit in the data generation part,and the sampling rate of 5GSPS,the vertical resolution of 12bit and the storage depth of 2Gpts in the data acquisition part.It communicates with the upper computer through the dualchannel PCIE interface.The medium rate system can realize data generation and acquisition through dual-channel.In the data generation part,it has an update rate of 250MSPS and vertical resolution of 16bit,and in the data acquisition part,it has a sampling rate of 300MSPS,a vertical resolution of 16bit and a storage depth of 512Mpts.Through the 10G Ethernet interface,it can communicate with the upper computer.In this thesis,following tasks are completed:1.According to the required parameters of the system,the design scheme of the system is determined and the selection of the key chips are completed.2.The hardware design of two systems is completed,including the design of ADC/DAC extension card and the design of multichannel of clock generator for JESD204B protocol.3.The FPGA logic design of two systems are completed.In the design of high rate system,the establishment of JESD204B link is completed,the 8-channel interboard transmission was realized based on the Aurora64B/66B protocol,and the large capacity storage of sampled data and dual channel PCIE communication are completed.In the design of the medium rate system,the design of 10G Ethernet communication is completed,and an optimization algorithm of LVDS source synchronous clock data sampling window based on IODELAY is proposed,which solves the problem of ADC sampling data deviation caused by different PCB wiring length and other factors.4.The software and hardware interaction protocol is formulated,and the upper computer application software development of the two systems is completed,as well as the integrated configuration software development of AXI_Lite and SPI for the two systems are completed.5.Actual testing of the two systems is completed,and the test results show that the designed two systems meet the design requirements.