Research On High Speed Multi-channel Analog To Digital Converter Acquisition And Channel Consistency Compensation

In radar systems,high-speed AD/DA acquisition playback is the bridge between antenna and signal processing.In recent years,with the development of radar systems,technologies such as active phased arrays and MIMO arrays have become the trend.The increase in the number of array elements and the increase in waveform bandwidth have placed higher demands on signal sampling techniques.The AD acquisition board is gradually moving toward multi-channel and high bandwidth.In recent years,the sampling rate of the AD converter and the amount of data generated per second have increased significantly.In order to reduce the timing control and wiring difficulty of high-speed,high-bitwidth parallel data transmission of traditional AD converters,major integrated circuit manufacturers began to use JESD204 B interface protocol as the preferred interface standard for high-speed converters.The encoded high-speed serial data is used instead of the original parallel sampling result.The data transfer rate also jumped from the traditional LVDS DDR interface of 500 Mbps to the CML interface of 12.5 Gbps.This also makes the digital-analog hybrid circuit design,inter-chip synchronization design,and signal integrity considerations of such converters very different from traditional converters.The main research contents of this thesis are:1.The design method of ultra-high-speed digital-analog hybrid circuit is studied,including place and route,power supply circuit design and signal integrity analysis.According to the content of the text,the sampling rate is up to 2.5GSPS,12-bit 8-channel ultra-high-speed synchronous AD acquisition circuit,and the hardware platform is built.2.Analyze the JESD204 B interface protocol and implement the interface design in the FPGA logic.Complete high-speed JESD204 B interface with serial interface speeds up to 6.5Gbps.And for the JESD204 B protocol content,different structure synchronous clock networks are proposed in various application scenarios.A complete multi-channel synchronous acquisition JESD204 B interface project is built in the software.3.Channel consistency compensation is studied.The compensation methods for narrowband and wideband are discussed separately.High-performance high-speed multi-channel simultaneous sampling technology is realized by a combination of "hard(synchronous clock network design)" and "soft(phase,delay compensation algorithm)".4.Analyze the cause of AD converter error and design a reasonable method for measuring the dynamic parameters of the converter.The performance of the high-speed synchronous acquisition circuit designed in this thesis is tested in detail.At the same time,the influence of circuit design on synchronization is discussed,and the sampling synchronization performance is measured to provide reference for similar designs in the future.