Research And Implementation Of Radar Clutter Simulation Based On DSP

When the radar detects the environmental target,it also receives the echo signals of other scatterers in the environment,which greatly increases the false alarm probability,which has a great influence on the radar detection accuracy.Therefore,simulating radar clutter data in different environments can greatly improve the radar's ability to identify and detect targets.With the advancement of electronic technology,the simulation requirements for the early radar system are getting higher and higher,including the amount of data and the speed of operation.Therefore,the accuracy and real-time of the clutter simulation are also higher.Due to the development of multi-core digital signal processor technology,its good flexibility and floating-point computing power,high real-time performance and high bit width memory bus can be well applied to the current requirements for clutter simulation,so multi-core DSP is used for radar.Clutter simulation has become an important research direction for clutter simulation.Based on several commonly used clutter models and simulation methods,this paper combines the multi-core digital signal processor TMS320C6678 to complete the clutter simulation.The details are as follows:First of all,this paper refers to the work done by domestic and foreign scholars on clutter simulation,and organizes and studies the research content of scholars.Then,the overall scheme of the simulation system is given and the characteristics of the clutter simulation hardware platform used in this simulation are briefly described.The process of multi-core system software development in CCS is described.The parallel model,the choice of inter-core communication and Several important parts to be considered in the development of multi-core system software such as data migration methods in multi-core systems,the characteristics of SYS/BIOS real-time operating system are clarified,and two components of SYS/BIOS are briefly described: thread module and synchronization module.Secondly,based on the clutter simulation principle and the DSP hardware platform,the design of the clutter simulation part is carried out,including the division of the system function module and the flow of the clutter simulation algorithm.The whole clutter simulation system is divided into communication and control modules and algorithm implementation modules.The communication and control module is mainly responsible for communication with the FPGA and the host computer,including instruction acquisition,current status receipt,and upload of clutter simulation data.The algorithm implementation module gives the implementation process according to the theoretical method,and carries out the multi-core parallel architecture design of the whole project,including the task,according to the specific task requirements of the clutter simulation,the different parallel processing models and the characteristics of different inter-core communication modes.The design of the distribution,master/slave kernel software threads,etc.,improves the execution efficiency of the task while ensuring the correctness of the clutter simulation results.At the end of the thesis,the test results of the system communication interface are given.The qualitative analysis and quantitative analysis of the clutter simulation data are carried out by using MATLAB.The time-consuming comparison between the single-core and multi-core execution is given,and the multi-core DSP is verified.The feasibility of implementing clutter simulation.