Design And Implementation Of High-speed Decision Feedback Equalizer And PRMLSD

With the proposal and development of cloud computing,5G, internet of things and other technologies, the data transfer rates of communication systems have become increasingly demanding. The nonidealities of High-speed transmission systems, such as channel high-frequency loss, reflection, crosstalk, noise, etc. iskey factors affecting data rate further improved. High-performance, low-cost equalizers can solve most of the problems caused by non-ideal factors, as a result, it has become the domestic and foreign high-speed communication systems research focus.This paper studies the design and implementation of the decision feedback equalization and partial response maximum likelihood sequence detection in lOGbps high-speed serial communication system. Firstly we introduced the modeling and implementation methods of serdes systems, which is based on decision feedback equalization, on different platforms (including Matlab, ADS) in detail, and includes a signal source, channel and DEF modules. The simulation compares DFE performance in various channel conditions and different data transmission rates. On this basis, a two-tap decision feedback equalization which works on the rate of rate of l0Gb/s is designed. In order to adapt to changes in channel conditions, the main tap of DFE is worked on an adaptive module, wherein the adaptive module uses a minimum mean square algorithm. Meanwhile, in order to meet the speed requirements, half-rate DFE structure is adopted. The decision feedback equalizer has been taped out, including a pad inside the chip area is 600μm× 550μm= 0.33mm2.Studies have shown that DFE meet most of the requirement at 10Gb/s data transfer rate conditions, but for higher data rates and more complex single channel conditions it can not meet the balance requirement.This paper also studied the modeling and implementation of partial response maximum likelihood sequence Detection Algorithm. PRMLSD is implemented by Viterbi algorithm, it mainly includes three modules:a branch metric unit, ACS unit and survivor information storage unit. In the process of decoding, PRML SD decoding using backtracking output. We finally completed PRMLSD logic synthesis and production of the corresponding logical netlist. This paper also studies the comparison between the DFE equalization performance and PRMLSD. Compared to the symbol and symbol detection (SSD) based DFE, PRML sequence detection can obtain a better performance based on Viterbi algorithm. Simulation results for 4 different channels show that PRML sequence detection can outperform conventional DFE with a detection gain of about 2-3dB. The performance of PRML equalization can be improved significantly especially when insertion loss is high.