Research On Concurrent Trace-based Debugging Under Multi-buffer Structure

Post-silicon verification is the important mean to eliminate bugs during chip’s design and manufacture flow. In post-silicon debug, now days, trace-based technique is widely used. With the appearance of network-on-chip, multi-core chip’s structure is becoming complicated and heterogeneous, which is a big challenge for trace-based post-silicon verification.Trace-based debug technology need to transfer and save trace data in on-chip trace buffer for analyzing off-line. With the increasing complexity of multi-core chips, it becomes a key problem to transfer concurrent trace data simultaneously under bandwidth constraint. To handle this, we propose a map-based self-regulation location selection (MSLS) algorithm in multi-buffer trace-based technology structure. This algorithm locates multiple trace buffers in interconnection fabrics under the bandwidth constraint and balances the distance between trace sources and trace buffers. Experimental results show that, our algorithm, compared to the prior method, can get about20%～40%buffer number reducing and nearly30%lesser energy consumption.In chip’s design flow, energy consumption is closely bounded up with chip’s reliability. Due to the high design complexity, today’s multi-core chips tend to high energy consumption, which brings the problem of chip reliability. In this article, aiming at medium scale NoC (about40-100cores), we will explore the multi-objective optimization with multi-buffer location and energy consumption in multi-buffer trace-based debug architecture. We show that the final result of multi-objective optimization with multi-buffer location and energy consumption is a situation of Pareto Optimality. For purpose of getting the Pareto Points of the buffer locations and energy consumption, we propose a genetic algorithm-based technique. Experimental results show that our technique is very efficient, which is a good reference to use multi-buffer trace-based debug architecture in post-silicon verification.Multi-buffer structure for trace-based debug is a new technique in post-silicon verification which has not been deeply explored. In this article, we analyze some difficult problems in using multi-buffer trace-based debug architecture in post-silicon verification. And we propose effective algorithms for multi-objective optimization with multi-buffer location and energy consumption. Our technique increase the reliability and practicality of multi-buffer trace-based debug structure, which has important significance for exploring new technique in the field of post-silicon verification.