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High-power Wideband Class F Power Amplifier Design And Debugging Strategies

Posted on:2011-10-06Degree:MasterType:Thesis
Country:ChinaCandidate:Z Y FuFull Text:PDF
GTID:2208360308967075Subject:Circuits and Systems
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Nowadays, the radio frequency integrated circuits (RFIC) and digital signal processing modules are usually integrated into portable electronics in order to ensure multimedia applications in small size. Some portable electronics such as cell-phones or base-stations are in an increasing pursuit of the efficiency to satisfy the requirement of long standby time and low cost, which depends on the power amplifier (PA) in these devices. So the high efficiency PA will draw much more attentions in the future research.In the research of high efficiency PAs, parasitic parameters analyzing and harmonics matching should be attached to the importance in order to satisfy the requirement of high efficiency and amplifying the constant-envelop signals in the telecommunication systems. As one type of the switched PAs, it's much easier for the Class-F PA to satisfy our requirement of high efficiency, so this dissertation focuses on the design of a broad-band, high-power Class-F PA.Firstly, the characteristics of switched PAs including the Class-D, Class-E, inverse Class-E (IE), Class-F and the inverse Class-F (IF) are introduced in this dissertation. Then, on the basis of the comprehensive analysis on the LDMOS power transistor MRFE6S9045N produced by Freescale, a broadband Class-F PA from 1.2GHz to 1.4GHz, 45W of output power and the efficiency up to 71% is simulated successfully in ADS environment. The main content of this dissertation follows as below:[1] On the basis of introduction of power transistors'technology development, the type selection of the transistor and the substrate are put on great emphasis before the design of the high efficiency PAs.[2] The structure characteristics and the design methodologies of the switched PAs are discussed, as well as the effect of the parasitic parameters in the high efficiency PA design.[3] Design methodologies of both impedance transformation networks at fundamental frequency and harmonics termination networks are discussed under the condition of 200MHz bandwidth, especially the second harmonic termination. Then, the input/output matching networks are designed. Finally, a Class-F PA from 1.2GHz to 1.4GHz, 45W of output power and the efficiency up to 71% is simulated successfully in ADS environment.[4] The debug process and the debug strategy analyzing of the broad-band Class-F PA in ADS environment are discussed in detail in this dissertation. The qualitative analysis and quantitative analysis on the debug process in ADS environment provide some reference to the real debug of the high efficiency PAs in practice, and reduce the difficulty of debugging at different circumstance of efficiency deterioration.
Keywords/Search Tags:Class-F PA, parasitic parameters, harmonic termination, debug strategy
PDF Full Text Request
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