Research And Engineering Of Terabit Router Port Switching Modules To Achieve

With the rapid growth of Internet's flow, existing routers won't meet switch and route demands in a short time. For this reason, to improve the performance of the routers further, T-bit routers will become indispensable equipments for interconnecting backbone network. Then switch architecture is the key factor of limiting routers' performance.The design of switch network mainly involves switch architecture, scheduling algorithm and queuing management mechanism. According to national 863 project "High performance IPv4/IPv6 router's basic platform and experiment system which can be extended to T-bit", this paper carried on a large number of work around the three aspects, and finally adopt PPS architecture with four layers for port switch model of T-bit router. At the same time, in every layer of PPS, we use CIOQ architecture with buffer queues at input and output ends. And Modified Weighted Deficit Round Robin (MWDRR) scheduling scheme and Random Early Discard (RED) queuing mechanism are applied at scheduling end.With switch capacity and switch speed increasing, it is inevitable to realize switch architecture with hardware in the hign-end router. So we select the XC2VP70 — 6FF1704C, the more advanced FPGAs of Xilinx, and realize the switch and scheduling function of our scheme. Then, considering the developing direction of high-end router in the future, external intrfaces of model all use standard parrel fiber interfaces, so have a strong portability. High speed PCB is also a design emphasis, and its quality directly decides the system performance.Switch architecture with hign performance and large capacity is essential for the development of hign-end router. So the reseach of this subject has applied value.