Researches On Switch Allocation And Buffer Optimization Techniques For High-performance Routers

From on-chip multi-core systems to high-performance computer systems,the interconnection network,as a fundamental component of communication between processing nodes,has been a bottleneck that limits system performance.A router is the infrastructure unit of the interconnection network and is responsible for forwarding packets in the network.It is a key component that affects network throughput and packet latency.The basic structure of the router includes input ports,buffers,switches and output ports.The buffer is used to store the packets waiting to be forwarded in the router,and the switch is responsible for forwarding the packets from the router input port to the output port without conflict.On-chip networks typically reduce the latency of packets passing through the router by simplifying the router's pipeline,while off-chip network routers support multi-port and high throughput by adding parallelism.Although the microarchitectures of routers vary for different networks,buffers and switches are always key components in routers.Designing efficient buffer architecture and switch allocation strategies can improve the performance of routers as well as the entire network.In this paper,buffer optimization methods and switch allocation strategies in the router are studied in depth.The main research points and innovations are as follows:1.Collaborative design of buffer optimization and switch allocationThe optimization of buffer architecture and switch allocation can effectively improve on-chip network performance.Existing methods independently optimize the buffer architecture and switch allocation,ignoring the interaction between the two parts.This paper proposes a collaborative design for existing buffer optimization strategies and switch allocation methods to further improve on-chip network performance.On the one hand,the Reorder Buffer technology is used to provide more effective requests for the switch allocation process,and on the other hand,the packets in the reorder buffer are dynamically selected by the switch allocation process to effectively alleviate congestion in the buffer.Through the collaborative design of switch allocation and buffer optimization,on-chip network performance can be effectively improved.2.A switch allocation method based on network congestion informationTraditional switch allocation methods only analyze the request information to make corresponding allocation decisions,while ignoring the impact of congestion in different ports on the switch allocation.In response to this deficiency,this paper designs Eca-Router,a new router microarchtecturre for on-chip networks.Eca-Router applies congestion information to the switch allocation process to improve the matching efficiency of switch allocation.This method further improves the efficiency of the switch allocation in the long-term dimension by avoiding the congestion of the port during the switch allocation process,significantly reducing the latency of the packet transmission and improving the network throughput.3.A switch allocation method based on endpoint congestion informationEndpoint congestion occurs when multiple data streams are sent to the same destination node.Endpoint congestion can form a saturation tree in the network and seriously affect network performance.Congestion avoidance mechanisms are commonly used in interconnect network to mitigate the impact of endpoint congestion,but endpoint congestion avoidance during switch assignment is rarely considered.This paper proposes a switch allocation method based on endpoint congestion information,which limits the request for endpoint congestion during the switch allocation process,thus alleviating the impact of endpoint congestion.The switch allocation method based on endpoint congestion information can effectively improve network performance by delaying the formation of endpoint congestion.4.An optimized design for intermediate buffers in high-radix routersHierarchical high-radix routers consist of many SRAM-based intermediate buffers.Although the hierarchical router architecture allows routers to efficiently support a large number of ports,small-capacity intermediate buffers can cause performance bottlenecks in high-radix routers.Increasing the capacity of the intermediate buffer can overcome this problem,but it requires a lot of SRAM buffer and brings a lot of hardware overhead.This paper proposes a new centralized intermediate buffer architecture and implements this architecture using the STT-MRAM buffer.Due to the high density and low static power consumption of STT-MRAM,our design can effectively improve the performance of high-radix routers without causing significant hardware overhead.5.An optimized design for input buffers in high-radix routersThe deepth of the input buffer in the high-radix router must be sized for the longest link in the network,but current high-performance systems use an asymmetric network to make the link length in the network vary greatly,resulting in a large number of input buffers being unused.Existing work has designed an input buffer architecture that allows ports to store packets in unused buffers on any other port.However,such a design introduces two virtual channels in the intermediate buffer,making the virtual channel too short and causing performance loss.This paper proposes a new input buffer architecture to effectively utilize idle input buffers without introducing redundant virtual channels in the intermediate buffer.This architecture allows free input buffers to be shared only between ports on the same tile.While reducing complex global logic circuits,it is ensured that the free input buffer can be fully utilized to improve network performance.6.Net Router Sim,a simulator for interconnect network router evaluationFor current on-chip and off-chip network performance evaluation,this paper implements the existing router optimization technologies,and a new simulator,Net Router Sim,targeted on the performance evaluation of the interconnection network router is formed.Net Router Sim completes the router microarchitecture and integrates new optimization strategies for different pipeline stages of the router,enabling high-performance router architecture design and collaborative design between different pipelines of routers to be performed more quickly and efficiently.Net Router Sim provides simulation environments for high-performance router designs.In summary,this paper focuses on the goal of "switch allocation and buffer optimization techniques for high-performance routers",based on the analysis of router architecture and interconnection network characteristics,optimizes the design of the router architecture,improves the switch allocation efficiency and buffer architecture,making router performance and overall interconnect network performance are greatly improved.Therefore,this paper solves some practical problems in the design of interconnected routers,and has certain engineering value and theoretical significance.