Research And Implementation Of Inter Frame Video Coding Technique

Inter frame coding is one of the most important part in video coding system, and contribute to the compression efficiency in a great measure. But the motion estimation and motion compensation in inter frame coding deal with large amount of data transmission and computation. It turns into a bottleneck in existing chip lock frequency and bandwidth of memory components. The problem can only be settled down by efficient VLSI architecture.Based on the research and analysis of lots of motion estimation algorithms, a new pyramid motion estimation algorithm and its VLSI architecture are proposed. It fully utilized the relativity of neighboring search window data to reduce bandwidth request. Compare to full search algorithm, the compression performance reduces extremely slightly, but hardware resource and computation time are largely saved.In view of that many fast algorithms don't suit for hardware realize, a motion estimation coprocessor based on MCU architecture is designed. This design makes use of the flexibility of MCU architecture, and adds some special instruction and processing structure to enhance the performance. It meets the real time request of complex algorithm through serial processing in overall construction and partial high speed parallel processing.The compensation in H.264 is much more complicate than ever before. Whether the interpolation construction is efficient directly impacts the real time performance of video codec. In this paper, we produced a high performance and parallel interpolation architecture. Reference data are reasonably divided into nine block rams, so that data can be read out in parallel. The experiment result shows that this architecture can meet the demand of H.264 HDTV time request.