Research And Design Of Low Noise Comparator For High Precision Analog To Digital Converter

Low power consumption,high speed and high precision are the three major directions of the research and design of the analog to digital converter(ADC).ADCs with different characteristics are suitable for different application environments.In recent years,in the rapidly developing fields of mobile communications,sensors,biomedicine,etc.,the requirements for accurate data information,high-quality audio and images are increasing,which requires high-precision ADCs to process weaker analog signals.As one of the core modules of the ADC,the accuracy,speed,stability and noise of the comparator play a key role in the performance of the overall circuit.By researching and analyzing several common structures of comparators,a comparator applied to SAR(Successive Approach Register)ADC is designed.First of all,this article introduces and analyzes several commonly used comparators.According to the characteristics of SAR ADC periodic quantization,discrete comparators are analyzed.However,because a single Latch comparator cannot achieve low noise,the comparator's structure adopts cascaded multi-stage preamplifier combined with StrongARM Latch,and analyzes its working principle and existing non-ideal factors.Based on this,in order to reduce these non-ideal factors,technical methods such as offset storage,correlated double sampling,and preamplifier are studied.By using these techniques in multi-stage comparators,the accuracy of the comparator is improved.Subsequently,the specifications of the SAR ADC on the comparator are analyzed,and the overall structure of the comparator is determined as a cascaded four-stage preamplifier combined with StrongARM Latch,the output offset storage is combined with the input offset storage.The specific modules such as preamplifier,dynamic latch,offset storage capacitor and common mode switch are analyzed and designed.Finally,based on the 130 nm CMOS process,the Cadence software was used to build and simulate the circuit,and the comparator was designed and post-simulated.The simulation results showed that the resolution of the comparator reached 0.5LSB(73 ?V)and the power consumption of a single cycle was 33.4 ?W.After using correlated double sampling and offset storage technology,the standard deviation of the equivalent input noise of the comparator is 89.95 ?V,the comparator can eliminate the input offset voltage of 5 mV,which meets the design specifications and is suitable for ADCs with an accuracy of 1LSB(146 ?V).