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Design Of CNN Oriented Energy-Efficient Analog Computing Unit

Posted on:2019-03-19Degree:MasterType:Thesis
Country:ChinaCandidate:T M ZhouFull Text:PDF
GTID:2428330596960776Subject:Microelectronics and Solid State Electronics
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Convolutional Neural Networks(CNN)has emerged as a fundamental technology for machine learning.High performance and high energy efficiency are essential for CNN processors,especially in mobile platforms such as autonomous vehicles,image recognition,and other internet of device.The main energy consumption of CNN comes from two aspects:(1)data access power consumption and reading and writing calculated data lead to dynamic power in long interconnected global bit lines,which brings a large power consumption;(2)multiplication and accumulation calculations power consumption.The Binarized Weight Network(BWN)has proved its high energy efficiency and nearly full accuracy recognition ability in many databases.Aiming at improving the energy efficiency problems above,this thesis focuses on research of a new vector multiplication and accumulation-calculation unit which is suitable for BWN.The main work and innovation in this thesis are as follows:(1)summarized main aspects of technical means of improving the energy efficiency of convolutional neural network at home and abroad,and analyzed the design techniques of several processing elements in CNN.Considering comprehensive indexes such as energy efficiency,area and the fault tolerance of neural network,vector multiplicative accumulation calculation has a great advantage in improving the energy efficiency of network.(2)designed a circuit structure of the voltage control analog vector multiplication and accumulation calculation unit by the integration of storage and calculation and reduces the computing power consumption by 32.7% compared to digital adders.(3)designed a dynamic tracking and adjusting Digital Low Dropout Regulator(DLDO)circuit which is no sensitive to global Process Voltage and Temperature(PVT)fluctuation.It produces three global control voltages of the analog computing array.Basing on the TSMC 28 nm CMOS process,the thesis designed analog multiplication and accumulation calculation PE array with a size of 28×28 and the peripheral processing circuit.The design is applied to CNN processor based on Alexnet network.PE array is configured different model to deal with convolution calculation of BWN.The simulation results show that,in the condition of typical corner at 25 degrees Celsius,peak energy efficiency reached 20.46TOPS/W.
Keywords/Search Tags:Convolutional Neural Networks, multiplication and accumulation, analog computing, Digital Low Dropout Regulator, energy-efficient
PDF Full Text Request
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