Low Power And Multi-precision Computing Circuits Design For Irregular Network Layers In Neural Networks

Convolutional Neural Network(CNN)has better robustness and fault tolerance.It is an important branch of Deep Learning(DL)and has been widely used in image recognition,speech recognition and text processing.As the CNN has a large number of multiply operations and a large amount of data,it is a huge challenge to the power consumption and memory access of the hardware.Traditional hardware design cannot meet the low power and high performance requirements of embedded devices.Aiming at the algorithm characteristics of convolutional neural network and satisfying the low power consumption and multi-precision requirements of chip design.An energy-efficient convolutional neural network accelerator based on digital-analog hybrid is designed in this thesis.Firstly,based on the spatial complexity of the network,a convolutional neural network design based on pruning and quantization is proposed.The pruning process is comparing the absolute value of kernel with the threshold and then pruning off the smaller convolution kernel.For the convolution layer with absolute value that uneven distribution,it can be trimmed more small convolution kernels and retained high-value convolution kernels to ensure the accuracy requirements.For the activation values,the bit width of the intermediate data is reduced by the quantization operation.And then,for the multiply-accumulate operation of the convolutional layer,the depthwise separable convolution is used to divide the standard convolution operation into two processes: depthwise convolution and pointwise convolution.Pointwise convolution can be regarded as 1×1 volume.The product is computed and implemented using an analog multiplier.In general,depthwise separable convolution can reduce network computation by about 9 times.After that,the simulation method is used to implement the operation of the irregular network layers.Based on the analog operation,digital-to-analog conversion and analog-to-digital conversion circuits are designed to realize the mutual conversion of digital and voltage.Finally,the design coefficient adjustable analog multiplier and analog adder realize the partial multiplication and addition of the convolutional neural network.The analog multiplier can greatly reduce the system power consumption and the accuracy loss is only 0.57%.The experimental results show that the accelerator designed in this thesis can achieve 5~8bit calculation for different CNN models under the TSMC 28 nm process.The power at 7bit and 0.9V only 0.43 mW,and the energy efficiency achieves 25.1TOPS/W.Compared with the mainstream designs,the CNN accelerator achieves 14 times improvement in energy efficiency.