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A Research Of Test Structure Based CMOS Process Reliability Evaluation Method

Posted on:2017-02-23Degree:MasterType:Thesis
Country:ChinaCandidate:Y LiuFull Text:PDF
GTID:2308330485488322Subject:Microelectronics and Solid State Electronics
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Reliability is the key whether integrated circuits are qualified as products or not, IC design house focuses heavily on reliability issues when designing chips. Fabrication plays the most important role in integrated circuit reliability, but circuit designers have very limited access to reliability data of the fabrication process, so it is crucial to develop an indirect fashion of evaluating IC reliability. Among many evaluation methods, teststructure based method utilizes test structures to evaluate the reliability performance of the fabrication process when designers cannot get comprehensive reliability data from foundry. Firstly, this thesis studied four most important CMOS process reliability issues, namely hot carrier injection(HCI), negative bias temperature instability(NBTI), timingdependent dielectric breakdown(TDDB) and electromigration, physical mechanisms of these issues as well as their impacts to integrated circuits were stated. Secondly, based on previous study, several test structure designs were proposed to test the four reliability issues studied before. The test structures can be divided into three categories: MOSFETs for HCI and NBTI test; MOS capacitors for TDDB test and metal lines for electromigration test. As the design of IC layouts must follow certain design rules, test structure design for different technologies can be time-consuming. To improve the efficiency of test structure design, a Python-based test structure layout library for CMOS process reliability evaluation was developed, which enabling the automatic generation of test structure layout. This layout library can generate test structures automatically according to the parameters assigned by designers. The Python source code could read in different process technology definition files and can be compiled into libraries for each process. The test structure generated by the library includes pads and interconnects, which improves the practicability of the library. Finally, alongside with a summury of test procedures for each reliability issues, an automatic test system based on semiconductor parameter analyzer was proposed, which provides the theoretical basis for the future automatic test system implementation.
Keywords/Search Tags:CMOS process, reliability, PCell, test structure, layout library
PDF Full Text Request
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